2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2014-01-08 20:18:29 +00:00
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/*
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* Xilinx MicroZED board DTS
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*
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2016-01-12 07:06:36 +00:00
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* Copyright (C) 2013 - 2016 Xilinx, Inc.
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2014-01-08 20:18:29 +00:00
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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model = "Zynq MicroZED Board";
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2018-07-12 04:10:19 +00:00
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compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
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2014-05-15 11:37:54 +00:00
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2014-05-15 11:37:55 +00:00
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aliases {
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serial0 = &uart1;
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2015-08-15 17:38:51 +00:00
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spi0 = &qspi;
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2016-01-12 07:06:36 +00:00
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mmc0 = &sdhci0;
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2014-05-15 11:37:55 +00:00
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};
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2016-11-11 12:11:37 +00:00
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memory@0 {
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2014-05-15 11:37:54 +00:00
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device_type = "memory";
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reg = <0 0x40000000>;
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};
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2016-01-12 07:06:36 +00:00
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chosen {
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bootargs = "earlyprintk";
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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2014-01-08 20:18:29 +00:00
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};
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2015-08-15 17:38:51 +00:00
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&qspi {
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2016-02-16 13:05:03 +00:00
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u-boot,dm-pre-reloc;
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2015-08-15 17:38:51 +00:00
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status = "okay";
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};
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2015-10-18 01:41:24 +00:00
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&uart1 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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2016-01-12 07:06:36 +00:00
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&sdhci0 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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};
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