2015-01-15 09:01:51 +00:00
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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2015-04-15 12:59:19 +00:00
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#include <asm/arch/clk.h>
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2015-01-15 09:01:51 +00:00
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long get_uart_clk(int dev_id)
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{
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u32 ver = zynqmp_get_silicon_version();
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switch (ver) {
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2015-04-15 12:59:19 +00:00
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case ZYNQMP_CSU_VERSION_VELOCE:
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return 48000;
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2015-01-15 09:01:51 +00:00
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case ZYNQMP_CSU_VERSION_EP108:
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return 25000000;
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}
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return 133000000;
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}
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#ifdef CONFIG_CLOCKS
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/**
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* set_cpu_clk_info() - Initialize clock framework
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* Always returns zero.
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*
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* This function is called from common code after relocation and sets up the
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* clock framework. The framework must not be used before this function had been
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* called.
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*/
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int set_cpu_clk_info(void)
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{
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gd->cpu_clk = get_tbclk();
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/* Support Veloce to show at least 1MHz via bdi */
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if (gd->cpu_clk > 1000000)
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
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else
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gd->bd->bi_arm_freq = 1;
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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#endif
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