u-boot/arch/arm/mach-imx/imx8ulp/lowlevel_init.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2020 NXP
 */

#include <config.h>

.align 8
.global rom_pointer
rom_pointer:
	.space 256

/*
 * Routine: save_boot_params (called after reset from start.S)
 */

.global save_boot_params
save_boot_params:
#ifndef CONFIG_SPL_BUILD
	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
	adr	x0, rom_pointer
	stp	x1, x2, [x0], #16
	stp	x3, x4, [x0], #16
#endif
	/* Returns */
	b	save_boot_params_ret
arm: imx: basic i.MX8ULP support Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-08-07 08:00:35 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
			`/*`
			`* Copyright 2020 NXP`
			`*/`

			`#include <config.h>`

			`.align 8`
			`.global rom_pointer`
			`rom_pointer:`
			`.space 256`

			`/*`
			`* Routine: save_boot_params (called after reset from start.S)`
			`*/`

			`.global save_boot_params`
			`save_boot_params:`
arm: imx8ulp: release and configure XRDC at early phase Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-08-07 08:00:55 +00:00			`#ifndef CONFIG_SPL_BUILD`
arm: imx: basic i.MX8ULP support Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-08-07 08:00:35 +00:00			`/* The firmware provided ATAG/FDT address can be found in r2/x0 */`
			`adr x0, rom_pointer`
			`stp x1, x2, [x0], #16`
			`stp x3, x4, [x0], #16`
arm: imx8ulp: release and configure XRDC at early phase Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-08-07 08:00:55 +00:00			`#endif`
arm: imx: basic i.MX8ULP support Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-08-07 08:00:35 +00:00			`/* Returns */`
			`b save_boot_params_ret`