2021-06-02 07:58:25 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_RK3568_COMMON_H
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#define __CONFIG_RK3568_COMMON_H
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2023-02-22 22:44:41 +00:00
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#define CFG_CPUID_OFFSET 0xa
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2021-06-02 07:58:25 +00:00
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#include "rockchip-common.h"
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2022-12-04 15:04:13 +00:00
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#define CFG_IRAM_BASE 0xfdcc0000
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2021-06-02 07:58:25 +00:00
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0
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2021-06-02 07:58:25 +00:00
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#define SDRAM_MAX_SIZE 0xf0000000
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00c00000\0" \
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2023-04-17 19:07:17 +00:00
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"script_offset_f=0xffe000\0" \
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"script_size_f=0x2000\0" \
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2021-06-02 07:58:25 +00:00
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"pxefile_addr_r=0x00e00000\0" \
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2023-12-26 16:43:30 +00:00
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"kernel_addr_r=0x02000000\0" \
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"kernel_comp_addr_r=0x0a000000\0" \
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"fdt_addr_r=0x12000000\0" \
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"fdtoverlay_addr_r=0x12100000\0" \
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"ramdisk_addr_r=0x12180000\0" \
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"kernel_comp_size=0x8000000\0"
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2021-06-02 07:58:25 +00:00
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2022-12-04 15:03:50 +00:00
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#define CFG_EXTRA_ENV_SETTINGS \
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2021-06-02 07:58:25 +00:00
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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2023-04-24 01:49:51 +00:00
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ROCKCHIP_DEVICE_SETTINGS \
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"boot_targets=" BOOT_TARGETS "\0"
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2021-06-02 07:58:25 +00:00
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#endif
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