u-boot/arch/riscv/cpu/generic/Kconfig

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>

config GENERIC_RISCV
	bool
	select ARCH_EARLY_INIT_R
	imply CPU
	imply CPU_RISCV
	imply RISCV_TIMER
	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
	imply CMD_CPU
	imply SPL_CPU_SUPPORT
	imply SPL_OPENSBI
	imply SPL_LOAD_FIT
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
			`#`
			`# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>`

riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-02-25 08:14:10 +00:00			`config GENERIC_RISCV`
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`bool`
riscv: Probe cpus during boot This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:34 +00:00			`select ARCH_EARLY_INIT_R`
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`imply CPU`
			`imply CPU_RISCV`
			`imply RISCV_TIMER`
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> 2019-08-21 19:14:43 +00:00			`imply SIFIVE_CLINT if (RISCV_MMODE \|\| SPL_RISCV_MMODE)`
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`imply CMD_CPU`
riscv: add SPL support U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> 2019-08-21 19:14:45 +00:00			`imply SPL_CPU_SUPPORT`
			`imply SPL_OPENSBI`
			`imply SPL_LOAD_FIT`