2013-05-12 22:40:54 +00:00
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/*
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* Copyright (C) 2012 Atmel Corporation.
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*
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* Static Memory Controllers (SMC) - System peripherals registers.
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* Based on SAMA5D3 datasheet.
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2013-05-12 22:40:54 +00:00
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*/
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#ifndef SAMA5D3_SMC_H
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#define SAMA5D3_SMC_H
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#ifdef __ASSEMBLY__
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#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
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#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
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#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
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2014-08-01 08:37:09 +00:00
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#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
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#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
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2013-05-12 22:40:54 +00:00
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#else
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struct at91_cs {
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u32 setup; /* 0x600 SMC Setup Register */
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u32 pulse; /* 0x604 SMC Pulse Register */
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u32 cycle; /* 0x608 SMC Cycle Register */
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u32 timings; /* 0x60C SMC Cycle Register */
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u32 mode; /* 0x610 SMC Mode Register */
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};
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struct at91_smc {
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2013-08-09 07:43:09 +00:00
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u32 reserved[384];
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2013-05-12 22:40:54 +00:00
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struct at91_cs cs[4];
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};
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#endif /* __ASSEMBLY__ */
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#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
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#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
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#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
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#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
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#define AT91_SMC_PULSE_NWE(x) (x & 0x3f)
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#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8)
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#define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16)
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#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24)
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#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
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#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
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#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf)
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#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4)
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#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8)
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#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12)
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#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16)
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#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24)
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#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28)
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#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31)
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#define AT91_SMC_MODE_RM_NCS 0x00000000
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#define AT91_SMC_MODE_RM_NRD 0x00000001
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#define AT91_SMC_MODE_WM_NCS 0x00000000
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#define AT91_SMC_MODE_WM_NWE 0x00000002
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#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
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#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
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#define AT91_SMC_MODE_EXNW_READY 0x00000030
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#define AT91_SMC_MODE_BAT 0x00000100
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#define AT91_SMC_MODE_DBW_8 0x00000000
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#define AT91_SMC_MODE_DBW_16 0x00001000
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#define AT91_SMC_MODE_DBW_32 0x00002000
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#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
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#define AT91_SMC_MODE_TDF 0x00100000
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#define AT91_SMC_MODE_PMEN 0x01000000
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#define AT91_SMC_MODE_PS_4 0x00000000
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#define AT91_SMC_MODE_PS_8 0x10000000
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#define AT91_SMC_MODE_PS_16 0x20000000
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#define AT91_SMC_MODE_PS_32 0x30000000
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#endif
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