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372 lines
14 KiB
C
372 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot gpio_defs.h
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*/
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#ifndef _ASM_INTEL_PINCTRL_DEFS_H_
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#define _ASM_INTEL_PINCTRL_DEFS_H_
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/* This file is included by device trees, so avoid BIT() macros */
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#define PAD_CFG0_TX_STATE_BIT 0
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#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
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#define PAD_CFG0_RX_STATE_BIT 1
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#define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT)
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#define PAD_CFG0_TX_DISABLE (1 << 8)
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#define PAD_CFG0_RX_DISABLE (1 << 9)
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#define PAD_CFG0_MODE_SHIFT 10
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#define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT)
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#define PAD_CFG0_ROUTE_MASK (0xf << 17)
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#define PAD_CFG0_ROUTE_NMI (1 << 17)
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#define PAD_CFG0_ROUTE_SMI (1 << 18)
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#define PAD_CFG0_ROUTE_SCI (1 << 19)
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#define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
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#define PAD_CFG0_RXTENCFG_MASK (3 << 21)
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#define PAD_CFG0_RXINV_MASK (1 << 23)
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#define PAD_CFG0_RX_POL_INVERT (1 << 23)
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#define PAD_CFG0_RX_POL_NONE (0 << 23)
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#define PAD_CFG0_PREGFRXSEL (1 << 24)
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#define PAD_CFG0_TRIG_MASK (3 << 25)
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#define PAD_CFG0_TRIG_LEVEL (0 << 25)
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#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
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#define PAD_CFG0_TRIG_OFF (2 << 25)
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#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
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#define PAD_CFG0_RXRAW1_MASK (1 << 28)
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#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29)
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#define PAD_CFG0_RESET_MASK (3 << 30)
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#define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30)
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#define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
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#define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
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#define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
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/*
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* Use the fourth bit in IntSel field to indicate gpio ownership. This field is
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* RO and hence not used during gpio configuration.
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*/
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#define PAD_CFG1_GPIO_DRIVER (0x1 << 4)
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#define PAD_CFG1_IRQ_MASK (0xff << 0)
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#define PAD_CFG1_IOSTERM_MASK (0x3 << 8)
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#define PAD_CFG1_IOSTERM_SAME (0x0 << 8)
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#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8)
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#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8)
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#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8)
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#define PAD_CFG1_PULL_MASK (0xf << 10)
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#define PAD_CFG1_PULL_NONE (0x0 << 10)
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#define PAD_CFG1_PULL_DN_5K (0x2 << 10)
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#define PAD_CFG1_PULL_DN_20K (0x4 << 10)
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#define PAD_CFG1_PULL_UP_1K (0x9 << 10)
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#define PAD_CFG1_PULL_UP_5K (0xa << 10)
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#define PAD_CFG1_PULL_UP_2K (0xb << 10)
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#define PAD_CFG1_PULL_UP_20K (0xc << 10)
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#define PAD_CFG1_PULL_UP_667 (0xd << 10)
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#define PAD_CFG1_PULL_NATIVE (0xf << 10)
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/* Tx enabled driving last value driven, Rx enabled */
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#define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14)
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/*
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* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
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* internally
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*/
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#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14)
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/*
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* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
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* internally
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*/
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#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14)
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/*
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* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
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* internally
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*/
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#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14)
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/*
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* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
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* internally
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*/
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#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14)
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/* Tx enabled driving 0, Rx enabled */
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#define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14)
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/* Tx enabled driving 1, Rx enabled */
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#define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14)
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/* Hi-Z, Rx driving 0 back to its controller internally */
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#define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14)
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/* Hi-Z, Rx driving 1 back to its controller internally */
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#define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14)
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/* Tx disabled, Rx enabled */
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#define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14)
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#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */
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/* mask to extract Iostandby bits */
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#define PAD_CFG1_IOSSTATE_MASK (0xf << 14)
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#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
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#define PAD_CFG2_DEBEN 1
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/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */
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#define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1)
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#define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1)
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#define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1)
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#define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1)
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#define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1)
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#define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1)
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#define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1)
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#define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1)
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#define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1)
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#define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1)
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#define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1)
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#define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1)
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#define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1)
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#define PAD_CFG2_DEBOUNCE_MASK 0x1f
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/* voltage tolerance 0=3.3V default 1=1.8V tolerant */
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#if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY)
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#define PAD_CFG1_TOL_MASK (0x1 << 25)
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#define PAD_CFG1_TOL_1V8 (0x1 << 25)
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#endif
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#define PAD_FUNC(value) PAD_CFG0_MODE_##value
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#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
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#define PAD_PULL(value) PAD_CFG1_PULL_##value
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#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
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#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
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#define PAD_IRQ_CFG(route, trig, inv) \
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(PAD_CFG0_ROUTE_##route | \
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PAD_CFG0_TRIG_##trig | \
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PAD_CFG0_RX_POL_##inv)
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#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
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#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \
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(PAD_CFG0_ROUTE_##route1 | \
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PAD_CFG0_ROUTE_##route2 | \
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PAD_CFG0_TRIG_##trig | \
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PAD_CFG0_RX_POL_##inv)
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#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
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#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
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__pad(__config0) (__config1)
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/* Native function configuration */
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#define PAD_CFG_NF(pad, pull, rst, func) \
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_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
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PAD_IOSSTATE(TX_LAST_RXE))
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#if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL)
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/*
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* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not
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* applicable to all SOCs. Refer EDS.
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*/
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#define PAD_CFG_NF_1V8(pad, pull, rst, func) \
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_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\
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PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8)
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#endif
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/* Native function configuration for standby state */
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#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
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_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
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PAD_IOSSTATE(iosstate))
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/*
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* Native function configuration for standby state, also configuring iostandby
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* as masked
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*/
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#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \
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_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
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PAD_IOSSTATE(IGNORE))
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/*
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* Native function configuration for standby state, also configuring iosstate
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* and iosterm
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*/
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#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
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PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
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/* General purpose output, no pullup/down */
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#define PAD_CFG_GPO(pad, val, rst) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
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PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE))
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/* General purpose output, with termination specified */
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#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
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PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE))
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/* General purpose output, no pullup/down */
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#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
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PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \
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PAD_CFG1_GPIO_DRIVER)
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/* General purpose output */
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#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
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PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
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/* General purpose input */
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#define PAD_CFG_GPI(pad, pull, rst) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
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PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
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/* General purpose input. The following macro sets the
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* Host Software Pad Ownership to GPIO Driver mode.
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*/
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#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
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PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
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#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_CFG0_RX_DISABLE, \
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PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \
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PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
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#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \
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PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
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/* GPIO Interrupt */
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#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \
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PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
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/*
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* No Connect configuration for unused pad.
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* Both TX and RX are disabled. RX disabling is done to avoid unnecessary
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* setting of GPI_STS.
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*/
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#define PAD_NC(pad, pull) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
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PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \
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PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
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/* General purpose input, routed to APIC */
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#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
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PAD_IOSSTATE(TXD_RXE))
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/* General purpose input, routed to APIC - with IOStandby Config*/
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#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
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PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
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/*
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* The following APIC macros assume the APIC will handle the filtering
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* on its own end. One just needs to pass an active high message into the
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* ITSS.
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*/
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#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
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PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
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#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
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PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
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#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
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PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
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/* General purpose input, routed to SMI */
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#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
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PAD_IOSSTATE(TXD_RXE))
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/* General purpose input, routed to SMI */
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#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
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PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
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#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
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PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
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||
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#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
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PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
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/* General purpose input, routed to SCI */
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||
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#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
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_PAD_CFG_STRUCT(pad, \
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||
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
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||
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PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
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||
|
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PAD_IOSSTATE(TXD_RXE))
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||
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||
|
|
/* General purpose input, routed to SCI */
|
||
|
|
#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
|
||
|
|
_PAD_CFG_STRUCT(pad, \
|
||
|
|
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
|
||
|
|
PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
|
||
|
|
PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
|
||
|
|
PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
|
||
|
|
PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \
|
||
|
|
_PAD_CFG_STRUCT_3(pad, \
|
||
|
|
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
|
||
|
|
PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
|
||
|
|
PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \
|
||
|
|
PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \
|
||
|
|
PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
|
||
|
|
|
||
|
|
/* General purpose input, routed to NMI */
|
||
|
|
#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
|
||
|
|
_PAD_CFG_STRUCT(pad, \
|
||
|
|
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
|
||
|
|
PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
|
||
|
|
PAD_IOSSTATE(TXD_RXE))
|
||
|
|
|
||
|
|
#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
|
||
|
|
/* GPI, GPIO Driver, SCI interrupt */
|
||
|
|
#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \
|
||
|
|
_PAD_CFG_STRUCT(pad, \
|
||
|
|
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
|
||
|
|
PAD_IRQ_CFG(SCI, trig, inv), \
|
||
|
|
PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
|
||
|
|
_PAD_CFG_STRUCT(pad, \
|
||
|
|
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
|
||
|
|
PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
|
||
|
|
PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
|
||
|
|
|
||
|
|
#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \
|
||
|
|
PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
|
||
|
|
|
||
|
|
#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
|
||
|
|
|
||
|
|
#endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */
|