mirror of
https://github.com/AsahiLinux/u-boot
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37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015-2017 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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* Copyright Google LLC 2019
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*
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* Modified from coreboot apollolake/include/soc/nvs.h
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*/
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#ifndef _GLOBAL_NVS_H_
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#define _GLOBAL_NVS_H_
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struct __packed acpi_global_nvs {
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/* Miscellaneous */
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u8 pcnt; /* 0x00 - Processor Count */
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u8 ppcm; /* 0x01 - Max PPC State */
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u8 lids; /* 0x02 - LID State */
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u8 pwrs; /* 0x03 - AC Power State */
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u8 dpte; /* 0x04 - Enable DPTF */
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u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */
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u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
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u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
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u64 nhla; /* 0x19 - 0x20 - NHLT Address */
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u32 nhll; /* 0x21 - 0x24 - NHLT Length */
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u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
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u8 scdp; /* 0x29 - SD_CD GPIO portid */
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u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
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u8 uior; /* 0x2b - UART debug controller init on S3 resume */
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u8 ecps; /* 0x2c - SGX Enabled status */
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u64 emna; /* 0x2d - 0x34 EPC base address */
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u64 elng; /* 0x35 - 0x3c EPC Length */
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u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
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u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
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};
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#endif /* _GLOBAL_NVS_H_ */
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