2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-01-14 13:21:52 +00:00
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/*
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* Copyright (c) 2014 Xilinx, Inc. Michal Simek
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* Copyright (c) 2004-2008 Texas Instruments
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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2019-01-22 22:09:26 +00:00
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MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
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LENGTH = IMAGE_MAX_SIZE }
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2014-01-14 13:21:52 +00:00
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = ALIGN(4);
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.text :
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{
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__image_copy_start = .;
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2014-08-07 12:26:43 +00:00
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*(.vectors)
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2014-01-14 13:21:52 +00:00
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CPUDIR/start.o (.text*)
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*(.text*)
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} > .sram
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. = ALIGN(4);
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.rodata : {
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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} > .sram
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. = ALIGN(4);
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.data : {
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*(.data*)
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} > .sram
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. = ALIGN(4);
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2015-10-18 01:41:23 +00:00
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.u_boot_list : {
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2016-03-15 21:56:29 +00:00
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KEEP(*(SORT(.u_boot_list*)));
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2015-10-18 01:41:23 +00:00
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} > .sram
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. = ALIGN(4);
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2014-01-14 13:21:52 +00:00
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2015-10-18 01:41:23 +00:00
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_image_binary_end = .;
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2014-01-14 13:21:52 +00:00
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_end = .;
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/* Move BSS section to RAM because of FAT */
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.bss (NOLOAD) : {
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end = .;
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} > .sdram
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/DISCARD/ : { *(.dynsym) }
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/DISCARD/ : { *(.dynstr*) }
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/DISCARD/ : { *(.dynamic*) }
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/DISCARD/ : { *(.plt*) }
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/DISCARD/ : { *(.interp*) }
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/DISCARD/ : { *(.gnu*) }
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}
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