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u-boot/arch/arm/mach-k3/include/mach/sys_proto.h

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ram: Introduce K3 AM654 DDR Sub System driver K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-02 14:21:02 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
void sdelay(unsigned long loops);
u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
u32 bound);
arm: k3: Add a wrapper to get tisci handle Create a wrapper to get the ti sci handle. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-03-08 06:17:33 +00:00
struct ti_sci_handle *get_ti_sci_handle(void);
arm: k3: Add support for updating msmc dt node Certain parts of msmc sram can be used by DMSC or can be marked as L3 cache. Since the available size can vary, changing DT every time the size varies might be painful. So, query this information using TISCI cmd and fixup the DT for kernel. Fixing up DT does the following: - Create a sram node if not available - update the reg property with available size - update ranges property - loop through available sub nodes and delete it if: - mentioned size is out if available range - subnode represents l3 cache or dmsc usage. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-03-08 06:17:34 +00:00
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
board: ti: am654: Use EEPROM-based board detection The TI AM654x EVM base board and the associated daughtercards have on- board I2C-based EEPROMs containing board configuration data. Use the board detection infrastructure introduced earlier to do the following: 1) Parse the AM654x EVM base board EEPROM and populate items like board name and MAC addresses into the TI common EEPROM data structure residing in SRAM scratch space 2) Check for presence of daughter card(s) by probing the associated presence signals via an I2C-based GPIO expander. Then, if such a card is found, parse the data such as additional Ethernet MAC addresses from its on-board EEPROM and populate into U-Boot accordingly 3) Dynamically create an U-Boot ENV variable called overlay_files containing a list of daugherboard-specific DTB overlays based on daughercards found. This patch adds support for the AM654x base board ("AM6-COMPROCEVM") as well as for the IDK ("AM6-IDKAPPEVM"), OLDI LCD ("OLDI-LCD1EVM") PCIe/USB3.0 ("SER-PCIEUSBEVM"), 2 Lane PCIe/USB2.0 ("SER-PCIE2LEVM"), and general purpuse ("AM6-GPAPPEVM") daughtercards. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-04 23:08:26 +00:00
int do_board_detect(void);
armv7R: K3: am654: Shut down R5 core after ATF startup on A53 Rather than simply parking the R5 core in WFE after starting up ATF on A53 instead use SYSFW API to properly shut down the R5 CPU cores as well as associated timer resources that were pre-allocated. This allows software further downstream to properly and gracefully bring the R5 cores back online if desired. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-07 13:54:42 +00:00
void release_resources_for_core_shutdown(void);
board: ti: am654: Disable TRNG node for HS devices On HS devices the access to TRNG is restricted on the non-secure ARM side, disable the node in DT to prevent firewall violations. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-17 21:15:40 +00:00
int fdt_disable_node(void *blob, char *node_path);
arm: mach-k3: j721e: Add detection for j721e Add an api soc_is_j721e(), and use it to enable certain functionality that is available only on j721e. This detection is needed when DT is not available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-05 17:14:19 +00:00
bool soc_is_j721e(void);
arm: mach-k3: j7200: Add support for SOC detection The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Add support for detection J7200 SoC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-05 17:14:21 +00:00
bool soc_is_j7200(void);
arm: mach-k3: j721e: Add detection for j721e Add an api soc_is_j721e(), and use it to enable certain functionality that is available only on j721e. This detection is needed when DT is not available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-05 17:14:19 +00:00
ram: Introduce K3 AM654 DDR Sub System driver K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-02 14:21:02 +00:00
#endif
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