mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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#ifndef __IMX8MM_ICORE_MX8MM_H
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#define __IMX8MM_ICORE_MX8MM_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SPL_MAX_SIZE (148 * 1024)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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# define CONFIG_SPL_STACK 0x920000
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# define CONFIG_SPL_BSS_START_ADDR 0x910000
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# define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
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# define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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# define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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# define CONFIG_MALLOC_F_ADDR 0x930000
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/* For RAW image gives a error info not panic */
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# define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 2) \
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func(MMC, mmc, 0)
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#include <config_distro_bootcmd.h>
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#undef CONFIG_ISO_PARTITION
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#else
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#define BOOTENV
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#endif
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#define ENV_MEM_LAYOUT_SETTINGS \
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"fdt_addr_r=0x44000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"ramdisk_addr_r=0x46400000\0" \
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"scriptaddr=0x46000000\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"console=ttymxc1,115200\0" \
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BOOTENV
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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/* SDRAM configuration */
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
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#define CONFIG_SYS_BOOTM_LEN SZ_256M
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END \
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(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
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/* UART */
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* USDHC */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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#endif /* __IMX8MM_ICORE_MX8MM_H */
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