arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM64 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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mcu_uart0: serial@4a00000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x04a00000 0x00 0x100>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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};
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mcu_uart1: serial@4a10000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x04a10000 0x00 0x100>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 160 0>;
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clock-names = "fclk";
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};
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mcu_i2c0: i2c@4900000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x04900000 0x00 0x100>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 106 2>;
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clock-names = "fck";
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};
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mcu_i2c1: i2c@4910000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x04910000 0x00 0x100>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 107 2>;
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clock-names = "fck";
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};
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mcu_spi0: spi@4b00000 {
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compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
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reg = <0x00 0x04b00000 0x00 0x400>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 147 0>;
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};
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mcu_spi1: spi@4b10000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x00 0x04b10000 0x00 0x400>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 148 0>;
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};
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2021-09-10 21:37:43 +00:00
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mcu_gpio_intr: interrupt-controller@4210000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x04210000 0x00 0x200>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <5>;
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ti,interrupt-ranges = <0 104 4>;
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};
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mcu_gpio0: gpio@4201000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x0 0x4201000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&mcu_gpio_intr>;
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interrupts = <30>, <31>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <23>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 79 0>;
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clock-names = "gpio";
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};
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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};
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