2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2010-10-07 21:48:45 +00:00
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/*
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2013-04-09 02:20:31 +00:00
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* (C) Copyright 2011 ARM Limited
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2010-10-07 21:48:45 +00:00
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* (C) Copyright 2010 Linaro
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* Matt Waddel, <matt.waddel@linaro.org>
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*
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* Configuration for Versatile Express. Parts were derived from other ARM
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* configurations.
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*/
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2013-04-09 02:20:31 +00:00
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#ifndef __VEXPRESS_COMMON_H
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#define __VEXPRESS_COMMON_H
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/*
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* Definitions copied from linux kernel:
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* arch/arm/mach-vexpress/include/mach/motherboard.h
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*/
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2021-09-10 06:19:19 +00:00
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#ifdef VEXPRESS_ORIGINAL_MEMORY_MAP
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2013-04-09 02:20:31 +00:00
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/* CS register bases for the original memory map. */
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#define V2M_PA_CS0 0x40000000
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#define V2M_PA_CS1 0x44000000
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#define V2M_PA_CS2 0x48000000
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#define V2M_PA_CS3 0x4c000000
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#define V2M_PA_CS7 0x10000000
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#define V2M_PERIPH_OFFSET(x) (x << 12)
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#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
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#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
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#define V2M_BASE 0x60000000
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#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
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/* CS register bases for the extended memory map. */
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#define V2M_PA_CS0 0x08000000
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#define V2M_PA_CS1 0x0c000000
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#define V2M_PA_CS2 0x14000000
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#define V2M_PA_CS3 0x18000000
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#define V2M_PA_CS7 0x1c000000
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#define V2M_PERIPH_OFFSET(x) (x << 16)
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#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
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#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
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#define V2M_BASE 0x80000000
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#endif
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/*
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* Physical addresses, offset from V2M_PA_CS0-3
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*/
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#define V2M_NOR0 (V2M_PA_CS0)
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#define V2M_NOR1 (V2M_PA_CS1)
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#define V2M_SRAM (V2M_PA_CS2)
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#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
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#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
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/* Common peripherals relative to CS7. */
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#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
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#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
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#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
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#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
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#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
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#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
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#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
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#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
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#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
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#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
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#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
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#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
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#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
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#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
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#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
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/* System register offsets. */
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#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
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#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
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#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
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/*
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* Configuration
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*/
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#define SYS_CFG_START (1 << 31)
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#define SYS_CFG_WRITE (1 << 30)
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#define SYS_CFG_OSC (1 << 20)
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#define SYS_CFG_VOLT (2 << 20)
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#define SYS_CFG_AMP (3 << 20)
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#define SYS_CFG_TEMP (4 << 20)
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#define SYS_CFG_RESET (5 << 20)
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#define SYS_CFG_SCC (6 << 20)
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#define SYS_CFG_MUXFPGA (7 << 20)
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#define SYS_CFG_SHUTDOWN (8 << 20)
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#define SYS_CFG_REBOOT (9 << 20)
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#define SYS_CFG_DVIMODE (11 << 20)
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#define SYS_CFG_POWER (12 << 20)
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#define SYS_CFG_SITE_MB (0 << 16)
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#define SYS_CFG_SITE_DB1 (1 << 16)
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#define SYS_CFG_SITE_DB2 (2 << 16)
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#define SYS_CFG_STACK(n) ((n) << 12)
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#define SYS_CFG_ERR (1 << 1)
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#define SYS_CFG_COMPLETE (1 << 0)
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2010-10-07 21:48:45 +00:00
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/* Board info register */
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2013-04-09 02:20:31 +00:00
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#define SYS_ID V2M_SYSREGS
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2010-10-07 21:48:45 +00:00
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2011-06-16 23:30:48 +00:00
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#define CONFIG_SYS_L2CACHE_OFF 1
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2011-03-28 09:59:07 +00:00
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2013-04-09 02:20:31 +00:00
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#define SCTL_BASE V2M_SYSCTL
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2010-10-07 21:48:45 +00:00
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#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
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2013-10-04 15:22:45 +00:00
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#define CONFIG_SYS_TIMER_RATE 1000000
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2013-11-17 15:17:42 +00:00
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#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
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2013-10-04 15:22:45 +00:00
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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2010-10-07 21:48:45 +00:00
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_CLOCK 24000000
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#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1}
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2013-04-09 02:20:31 +00:00
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#define CONFIG_SYS_SERIAL0 V2M_UART0
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#define CONFIG_SYS_SERIAL1 V2M_UART1
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2010-10-07 21:48:45 +00:00
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2011-04-16 11:54:08 +00:00
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
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2010-10-07 21:48:45 +00:00
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Miscellaneous configurable options */
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2013-04-09 02:20:31 +00:00
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#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
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2010-10-07 21:48:45 +00:00
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/* Physical Memory Map */
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2013-04-09 02:20:31 +00:00
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#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
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#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
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((unsigned int)0x20000000))
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2010-10-07 21:48:45 +00:00
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
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#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
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/* additions for new relocation code */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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2010-10-26 11:32:32 +00:00
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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2010-10-07 21:48:45 +00:00
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
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2010-10-26 11:32:32 +00:00
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CONFIG_SYS_INIT_RAM_SIZE - \
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2010-10-26 12:34:52 +00:00
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GENERATED_GBL_DATA_SIZE)
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2010-10-07 21:48:45 +00:00
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
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2015-06-28 19:05:12 +00:00
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2010-10-07 21:48:45 +00:00
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/* Basic environment settings */
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2015-06-28 19:05:12 +00:00
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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2013-04-09 02:20:31 +00:00
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ARM: vexpress_ca9x4: Reintroduce board in order to use with QEMU.
vexpress_ca9x4 is seemingly the only board except for qemu_arm which
is able to run U-Boot correctly, using the `-M vexpress-a9` option to
QEMU. Building for qemu_arm and running qemu-system-arm with the `-M
virt` argument has a number of downsides, most importantly that it
only supports virtio storage drivers. This significantly reduces its
usefulness in testing memory card and Flash solutions, especially when
the tested images are from a third party source.
So therefore we reintroduce the vexpress_ca9x4 board in this commit,
with the explicit goal of using it with QEMU.
A number of differences to note from the original:
* Since the board was apparently unmaintained, I have now set myself
as the maintainer.
* The board has been converted to use the driver model, which was the
reason it was removed in the first place.
* The vexpress_ca15_tc2 and vexpress_ca5x2 boards, which were removed
in the same commit, are not necessary for the QEMU use case, and
have been omitted.
* An `mmc0` alias was introduced in the dts file. The mmc is not
detected correctly without this, now that it's based on the device
tree instead of the board's init function.
* A couple of other nodes were removed because they were problematic
when trying to run the UEFI bootmgr. Once again, the primary use
case here is QEMU, and these nodes are not needed for that to work.
* Unnecessary board init code has been removed, thanks to driver model
and device tree.
* `CONFIG_OF_EMBED` has been enabled. I know this goes against
recommended practice, but there doesn't seem to be any other way to
pass the dtb to U-Boot in the QEMU scenario. Using the -dtb argument
does not work, I suppose because U-Boot doesn't use the same
mechanics as the kernel when it's booting.
* Load addresses have been changed to fit QEMU use case.
People wanting to get a more detailed, yet somewhat isolated, diff
between this and the original, can run this command:
git diff c6c26a05b89f25a06e7562f8c2071b60fd0c9eac~1 -- \
$( git diff-tree --diff-filter=A -r --name-only HEAD~1 HEAD)
(Make sure to either check out this commit first, or replace HEAD with
the commit ID of this commit)
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
2021-09-07 06:37:51 +00:00
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"kernel_addr_r=0x60100000\0" \
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"fdt_addr_r=0x60000000\0" \
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"bootargs=console=tty0 console=ttyAMA0,38400n8\0" \
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2015-06-28 19:05:12 +00:00
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BOOTENV \
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2010-10-07 21:48:45 +00:00
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"console=ttyAMA0,38400n8\0" \
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"dram=1024M\0" \
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"root=/dev/sda1 rw\0" \
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"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
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"24M@0x2000000(initrd)\0" \
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"flashargs=setenv bootargs root=${root} console=${console} " \
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"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
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"devtmpfs.mount=0 vmalloc=256M\0" \
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"bootflash=run flashargs; " \
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2011-08-23 11:06:59 +00:00
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"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
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2020-02-25 17:22:16 +00:00
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"bootm ${kernel_addr} ${ramdisk_addr_r}\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
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2010-10-07 21:48:45 +00:00
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/* FLASH and environment organization */
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#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
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#define CONFIG_SYS_FLASH_SIZE 0x04000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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2013-04-09 02:20:31 +00:00
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#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
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#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
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2010-10-07 21:48:45 +00:00
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
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/* Timeout values in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
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/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
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#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
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#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
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/* Room required on the stack for the environment data */
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/*
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* Amount of flash used for environment:
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* We don't know which end has the small erase blocks so we use the penultimate
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* sector location for the environment
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*/
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/* Store environment at top of flash */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
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CONFIG_SYS_FLASH_BASE1 }
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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2013-04-09 02:20:31 +00:00
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#endif /* VEXPRESS_COMMON_H */
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