mirror of
https://github.com/AsahiLinux/u-boot
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187 lines
4.1 KiB
C
187 lines
4.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <env.h>
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#include <env_internal.h>
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#include <i2c_eeprom.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include "lpddr4_timing.h"
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DECLARE_GLOBAL_DATA_PTR;
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int mach_cpu_init(void)
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{
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icache_enable();
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return 0;
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}
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int board_phys_sdram_size(phys_size_t *size)
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{
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const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
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u8 memcfg = dh_get_memcfg();
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*size = (u64)memsz[memcfg] << 20ULL;
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return 0;
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}
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/* IMX8M SNVS registers needed for the bootcount functionality */
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#define SNVS_BASE_ADDR 0x30370000
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#define SNVS_LPSR 0x4c
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#define SNVS_LPLVDR 0x64
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#define SNVS_LPPGDR_INIT 0x41736166
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static void setup_snvs(void)
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{
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/* Enable SNVS clock */
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clock_enable(CCGR_SNVS, 1);
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/* Initialize glitch detect */
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writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
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/* Clear interrupt status */
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writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
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}
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static void setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Set INTF as RGMII, enable RGMII TXC clock. */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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set_clk_eqos(ENET_125MHZ);
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}
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output. */
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setbits_le32(&gpr->gpr[1], BIT(22));
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set_clk_enet(ENET_125MHZ);
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}
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static int setup_mac_address_from_eeprom(char *alias, char *env, bool odd)
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{
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unsigned char enetaddr[6];
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struct udevice *dev;
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int ret, offset;
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offset = fdt_path_offset(gd->fdt_blob, alias);
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if (offset < 0) {
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printf("%s: No eeprom0 path offset\n", __func__);
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return offset;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, offset, &dev);
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if (ret) {
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printf("Cannot find EEPROM!\n");
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return ret;
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}
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ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
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if (ret) {
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printf("Error reading configuration EEPROM!\n");
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return ret;
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}
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/*
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* Populate second ethernet MAC from first ethernet EEPROM with MAC
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* address LSByte incremented by 1. This is only used on SoMs without
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* second ethernet EEPROM, i.e. early prototypes.
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*/
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if (odd)
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enetaddr[5]++;
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eth_env_set_enetaddr(env, enetaddr);
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return 0;
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}
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static void setup_mac_address(void)
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{
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unsigned char enetaddr[6];
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bool skip_eth0 = false;
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bool skip_eth1 = false;
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int ret;
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ret = eth_env_get_enetaddr("ethaddr", enetaddr);
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if (ret) /* ethaddr is already set */
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skip_eth0 = true;
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ret = eth_env_get_enetaddr("eth1addr", enetaddr);
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if (ret) /* eth1addr is already set */
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skip_eth1 = true;
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/* Both MAC addresses are already set in U-Boot environment. */
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if (skip_eth0 && skip_eth1)
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return;
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/*
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* If IIM fuses contain valid MAC address, use it.
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* The IIM MAC address fuses are NOT programmed by default.
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*/
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imx_get_mac_from_fuse(0, enetaddr);
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if (is_valid_ethaddr(enetaddr)) {
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if (!skip_eth0)
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eth_env_set_enetaddr("ethaddr", enetaddr);
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/*
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* The LSbit of MAC address in fuses is always 0, use the
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* next consecutive MAC address for the second ethernet.
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*/
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enetaddr[5]++;
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if (!skip_eth1)
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eth_env_set_enetaddr("eth1addr", enetaddr);
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return;
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}
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/* Use on-SoM EEPROMs with pre-programmed MAC address. */
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if (!skip_eth0) {
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/* We cannot do much more if this returns -ve . */
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setup_mac_address_from_eeprom("eeprom0", "ethaddr", false);
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}
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if (!skip_eth1) {
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ret = setup_mac_address_from_eeprom("eeprom1", "eth1addr",
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false);
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if (ret) { /* Second EEPROM might not be populated. */
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/* We cannot do much more if this returns -ve . */
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setup_mac_address_from_eeprom("eeprom0", "eth1addr",
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true);
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}
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}
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}
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int board_init(void)
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{
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setup_eqos();
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setup_fec();
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setup_snvs();
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return 0;
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}
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int board_late_init(void)
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{
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setup_mac_address();
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return 0;
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}
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enum env_location env_get_location(enum env_operation op, int prio)
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{
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return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
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}
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