2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2018-03-09 03:39:26 +00:00
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/*
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* Copyright (C) 2018 Intel Corporation
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*/
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#include "socfpga_stratix10.dtsi"
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/ {
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model = "SoCFPGA Stratix 10 SoCDK";
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aliases {
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2019-11-21 14:06:12 +00:00
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ethernet0 = &gmac0;
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2019-06-13 08:17:23 +00:00
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i2c0 = &i2c1;
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2018-03-09 03:39:26 +00:00
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory {
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2019-11-08 02:56:26 +00:00
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#address-cells = <2>;
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#size-cells = <2>;
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2018-03-09 03:39:26 +00:00
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device_type = "memory";
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arm: dts: Stratix10: Modify stratix10 socdk memory node
The stratix10 socdk ships with 4GB of memory. Modify the
device tree to represent this. Note that to access 4GB of
memory in Stratix 10, due to the IO space from 2GB to 4GB,
we use the fact that the DDR controller ignores upper address
bits outside of the configured DRAM's size. This means that
, the 4GB DRAM is mapped to memory every 4GB.
For an 8GB memory, you can either live with the 2GB IO space,
and loose access to that memory from the processor, or use
the same trick:
Loose 2GB of memory:
memory {
device_type = "memory";
/* 8GB */
/* first 2GB */
reg = <0 0x00000000 0 0x80000000>,
/* last 4GB */
<1 0x00000000 1 0x00000000>;
u-boot,dm-pre-reloc;
};
or to map it all:
memory {
device_type = "memory";
/* 8GB */
/* first 2GB */
reg = <0 0x00000000 0 0x80000000>,
/* next 6GB */
<2 0x80000000 1 0x80000000>;
u-boot,dm-pre-reloc;
};
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-03-21 17:24:03 +00:00
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/* 4GB */
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reg = <0 0x00000000 0 0x80000000>,
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<1 0x80000000 0 0x80000000>;
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2018-07-12 11:13:33 +00:00
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u-boot,dm-pre-reloc;
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2018-03-09 03:39:26 +00:00
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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max-frame-size = <3800>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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2019-11-21 14:48:56 +00:00
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txc-skew-ps = <900>; /* 0ps */
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2018-03-09 03:39:26 +00:00
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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};
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};
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};
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2019-06-13 08:17:23 +00:00
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&i2c1 {
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status = "okay";
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};
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2018-03-09 03:39:26 +00:00
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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2018-05-18 14:05:35 +00:00
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cap-mmc-highspeed;
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2018-03-09 03:39:26 +00:00
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broken-cd;
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bus-width = <4>;
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2018-05-18 14:05:35 +00:00
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drvsel = <3>;
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2022-05-24 07:02:28 +00:00
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smplsel = <2>;
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2018-03-09 03:39:26 +00:00
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};
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2019-04-03 05:45:02 +00:00
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&qspi {
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00a";
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reg = <0>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <1>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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qspi_boot: partition@0 {
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label = "Boot and fpga data";
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reg = <0x0 0x4000000>;
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};
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qspi_rootfs: partition@4000000 {
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label = "Root Filesystem - JFFS2";
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reg = <0x4000000 0x4000000>;
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};
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};
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};
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};
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2018-03-09 03:39:26 +00:00
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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