2002-08-16 13:30:52 +00:00
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/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| File Name: enetemac.h
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| Function: Header file for the EMAC3 macro on the 405GP.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 29-Apr-99 Created MKW
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+----------------------------------------------------------------------------*/
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#ifndef _enetemac_h_
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#define _enetemac_h_
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2004-06-06 23:53:59 +00:00
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#include <net.h>
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#include <405_mal.h>
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2002-08-16 13:30:52 +00:00
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/*-----------------------------------------------------------------------------+
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| General enternet defines. 802 frames are not supported.
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+-----------------------------------------------------------------------------*/
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#define ENET_ADDR_LENGTH 6
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#define ENET_ARPTYPE 0x806
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#define ARP_REQUEST 1
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#define ARP_REPLY 2
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#define ENET_IPTYPE 0x800
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#define ARP_CACHE_SIZE 5
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struct enet_frame {
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unsigned char dest_addr[ENET_ADDR_LENGTH];
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unsigned char source_addr[ENET_ADDR_LENGTH];
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unsigned short type;
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unsigned char enet_data[1];
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};
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struct arp_entry {
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unsigned long inet_address;
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unsigned char mac_address[ENET_ADDR_LENGTH];
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unsigned long valid;
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unsigned long sec;
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unsigned long nsec;
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};
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/*Register addresses */
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#if defined(CONFIG_440)
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#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
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#define ZMII_FER (ZMII_BASE)
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#define ZMII_SSR (ZMII_BASE + 4)
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#define ZMII_SMIISR (ZMII_BASE + 8)
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#define ZMII_RMII 0x22000000
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#define ZMII_MDI0 0x80000000
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#endif /* CONFIG_440 */
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#if defined(CONFIG_440)
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#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
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#else
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#define EMAC_BASE 0xEF600800
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#endif
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#define EMAC_M0 (EMAC_BASE)
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#define EMAC_M1 (EMAC_BASE + 4)
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#define EMAC_TXM0 (EMAC_BASE + 8)
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#define EMAC_TXM1 (EMAC_BASE + 12)
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#define EMAC_RXM (EMAC_BASE + 16)
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#define EMAC_ISR (EMAC_BASE + 20)
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#define EMAC_IER (EMAC_BASE + 24)
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#define EMAC_IAH (EMAC_BASE + 28)
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#define EMAC_IAL (EMAC_BASE + 32)
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#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
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#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
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#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
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#define EMAC_IND_HASH_1 (EMAC_BASE + 48)
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#define EMAC_IND_HASH_2 (EMAC_BASE + 52)
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#define EMAC_IND_HASH_3 (EMAC_BASE + 56)
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#define EMAC_IND_HASH_4 (EMAC_BASE + 60)
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#define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
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#define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
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#define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
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#define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
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#define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
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#define EMAC_LST_SRC_HI (EMAC_BASE + 84)
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#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
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#define EMAC_STACR (EMAC_BASE + 92)
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#define EMAC_TRTR (EMAC_BASE + 96)
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#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
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/* bit definitions */
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/* MODE REG 0 */
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#define EMAC_M0_RXI 0x80000000
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#define EMAC_M0_TXI 0x40000000
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#define EMAC_M0_SRST 0x20000000
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#define EMAC_M0_TXE 0x10000000
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#define EMAC_M0_RXE 0x08000000
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#define EMAC_M0_WKE 0x04000000
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/* MODE Reg 1 */
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#define EMAC_M1_FDE 0x80000000
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#define EMAC_M1_ILE 0x40000000
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#define EMAC_M1_VLE 0x20000000
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#define EMAC_M1_EIFC 0x10000000
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#define EMAC_M1_APP 0x08000000
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#define EMAC_M1_AEMI 0x02000000
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#define EMAC_M1_IST 0x01000000
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#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
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#define EMAC_M1_MF_100MBPS 0x00400000
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#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
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#define EMAC_M1_RFS_2K 0x00200000
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#define EMAC_M1_RFS_1K 0x00100000
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#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
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#define EMAC_M1_TX_FIFO_1K 0x00040000
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#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
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#define EMAC_M1_TR0_MULTI 0x00008000
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#define EMAC_M1_TR1_DEPEND 0x00004000
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#define EMAC_M1_TR1_MULTI 0x00002000
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#define EMAC_M1_JUMBO_ENABLE 0x00001000
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/* Transmit Mode Register 0 */
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#define EMAC_TXM0_GNP0 0x80000000
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#define EMAC_TXM0_GNP1 0x40000000
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#define EMAC_TXM0_GNPD 0x20000000
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#define EMAC_TXM0_FC 0x10000000
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/* Receive Mode Register */
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#define EMAC_RMR_SP 0x80000000
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#define EMAC_RMR_SFCS 0x40000000
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#define EMAC_RMR_ARRP 0x20000000
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#define EMAC_RMR_ARP 0x10000000
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#define EMAC_RMR_AROP 0x08000000
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#define EMAC_RMR_ARPI 0x04000000
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#define EMAC_RMR_PPP 0x02000000
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#define EMAC_RMR_PME 0x01000000
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#define EMAC_RMR_PMME 0x00800000
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#define EMAC_RMR_IAE 0x00400000
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#define EMAC_RMR_MIAE 0x00200000
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#define EMAC_RMR_BAE 0x00100000
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#define EMAC_RMR_MAE 0x00080000
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/* Interrupt Status & enable Regs */
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#define EMAC_ISR_OVR 0x02000000
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#define EMAC_ISR_PP 0x01000000
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#define EMAC_ISR_BP 0x00800000
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#define EMAC_ISR_RP 0x00400000
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#define EMAC_ISR_SE 0x00200000
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#define EMAC_ISR_SYE 0x00100000
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#define EMAC_ISR_BFCS 0x00080000
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#define EMAC_ISR_PTLE 0x00040000
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#define EMAC_ISR_ORE 0x00020000
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#define EMAC_ISR_IRE 0x00010000
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#define EMAC_ISR_DBDM 0x00000200
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#define EMAC_ISR_DB0 0x00000100
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#define EMAC_ISR_SE0 0x00000080
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#define EMAC_ISR_TE0 0x00000040
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#define EMAC_ISR_DB1 0x00000020
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#define EMAC_ISR_SE1 0x00000010
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#define EMAC_ISR_TE1 0x00000008
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#define EMAC_ISR_MOS 0x00000002
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#define EMAC_ISR_MOF 0x00000001
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/* STA CONTROL REG */
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#define EMAC_STACR_OC 0x00008000
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#define EMAC_STACR_PHYE 0x00004000
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#define EMAC_STACR_WRITE 0x00002000
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#define EMAC_STACR_READ 0x00001000
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#define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */
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#define EMAC_STACR_CLK_66MHZ 0x00000400
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#define EMAC_STACR_CLK_100MHZ 0x00000C00
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/* Transmit Request Threshold Register */
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#define EMAC_TRTR_256 0x18000000 /* 0's for 64 Bytes */
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#define EMAC_TRTR_192 0x10000000
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#define EMAC_TRTR_128 0x01000000
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/* the follwing defines are for the MadMAL status and control registers. */
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/* For bits 0..5 look at the mal.h file */
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#define EMAC_TX_CTRL_GFCS 0x0200
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#define EMAC_TX_CTRL_GP 0x0100
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#define EMAC_TX_CTRL_ISA 0x0080
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#define EMAC_TX_CTRL_RSA 0x0040
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#define EMAC_TX_CTRL_IVT 0x0020
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#define EMAC_TX_CTRL_RVT 0x0010
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#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
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#define EMAC_TX_ST_BFCS 0x0200
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#define EMAC_TX_ST_BPP 0x0100
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#define EMAC_TX_ST_LCS 0x0080
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#define EMAC_TX_ST_ED 0x0040
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#define EMAC_TX_ST_EC 0x0020
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#define EMAC_TX_ST_LC 0x0010
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#define EMAC_TX_ST_MC 0x0008
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#define EMAC_TX_ST_SC 0x0004
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#define EMAC_TX_ST_UR 0x0002
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#define EMAC_TX_ST_SQE 0x0001
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#define EMAC_TX_ST_DEFAULT 0x03F3
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/* madmal receive status / Control bits */
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#define EMAC_RX_ST_OE 0x0200
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#define EMAC_RX_ST_PP 0x0100
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#define EMAC_RX_ST_BP 0x0080
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#define EMAC_RX_ST_RP 0x0040
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#define EMAC_RX_ST_SE 0x0020
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#define EMAC_RX_ST_AE 0x0010
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#define EMAC_RX_ST_BFCS 0x0008
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#define EMAC_RX_ST_PTL 0x0004
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#define EMAC_RX_ST_ORE 0x0002
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#define EMAC_RX_ST_IRE 0x0001
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/* all the errors we care about */
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#define EMAC_RX_ERRORS 0x03FF
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2004-06-06 23:53:59 +00:00
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#define NUM_RX_BUFF PKTBUFSRX
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#define NUM_TX_BUFF 1
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#define MAX_ERR_LOG 10
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typedef struct emac_stats_st{ /* Statistic Block */
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int data_len_err;
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int rx_frames;
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int rx;
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int rx_prot_err;
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int int_err;
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int pkts_tx;
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int pkts_rx;
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int pkts_handled;
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short tx_err_log[MAX_ERR_LOG];
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short rx_err_log[MAX_ERR_LOG];
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} EMAC_STATS_ST, *EMAC_STATS_PST;
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/* Structure containing variables used by the shared code (440gx_enet.c) */
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typedef struct emac_440gx_hw_st {
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uint32_t hw_addr; /* EMAC offset */
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uint32_t tah_addr; /* TAH offset */
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uint32_t phy_id;
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uint32_t phy_addr;
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uint32_t original_fc;
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uint32_t txcw;
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uint32_t autoneg_failed;
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uint32_t emac_ier;
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volatile mal_desc_t *tx;
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volatile mal_desc_t *rx;
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bd_t *bis; /* for eth_init upon mal error */
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mal_desc_t *alloc_tx_buf;
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mal_desc_t *alloc_rx_buf;
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char *txbuf_ptr;
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uint16_t devnum;
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int get_link_status;
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int tbi_compatibility_en;
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int tbi_compatibility_on;
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int fc_send_xon;
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int report_tx_early;
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int first_init;
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int tx_err_index;
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int rx_err_index;
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int rx_slot; /* MAL Receive Slot */
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int rx_i_index; /* Receive Interrupt Queue Index */
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int rx_u_index; /* Receive User Queue Index */
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int tx_slot; /* MAL Transmit Slot */
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int tx_i_index; /* Transmit Interrupt Queue Index */
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int tx_u_index; /* Transmit User Queue Index */
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int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
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int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
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int is_receiving; /* sync with eth interrupt */
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int print_speed; /* print speed message upon start */
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EMAC_STATS_ST stats;
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} EMAC_405_HW_ST, *EMAC_405_HW_PST;
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2002-08-16 13:30:52 +00:00
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/*-----------------------------------------------------------------------------+
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| Function prototypes for device table.
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+-----------------------------------------------------------------------------*/
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#endif /* _enetLib_h_ */
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