2019-02-25 08:15:19 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <common.h>
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#include <dm.h>
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2020-05-10 17:40:03 +00:00
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#include <env.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2020-05-10 17:40:08 +00:00
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#include <linux/bug.h>
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2019-06-25 06:31:44 +00:00
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#include <linux/delay.h>
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#include <linux/io.h>
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#ifdef CONFIG_MISC_INIT_R
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#define FU540_OTP_BASE_ADDR 0x10070000
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struct fu540_otp_regs {
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u32 pa; /* Address input */
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u32 paio; /* Program address input */
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u32 pas; /* Program redundancy cell selection input */
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u32 pce; /* OTP Macro enable input */
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u32 pclk; /* Clock input */
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u32 pdin; /* Write data input */
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u32 pdout; /* Read data output */
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u32 pdstb; /* Deep standby mode enable input (active low) */
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u32 pprog; /* Program mode enable input */
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u32 ptc; /* Test column enable input */
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u32 ptm; /* Test mode enable input */
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u32 ptm_rep;/* Repair function test mode enable input */
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u32 ptr; /* Test row enable input */
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u32 ptrim; /* Repair function enable input */
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u32 pwe; /* Write enable input (defines program cycle) */
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} __packed;
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#define BYTES_PER_FUSE 4
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#define NUM_FUSES 0x1000
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static int fu540_otp_read(int offset, void *buf, int size)
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{
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struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
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unsigned int i;
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int fuseidx = offset / BYTES_PER_FUSE;
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int fusecount = size / BYTES_PER_FUSE;
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u32 fusebuf[fusecount];
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/* check bounds */
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if (offset < 0 || size < 0)
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return -EINVAL;
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if (fuseidx >= NUM_FUSES)
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return -EINVAL;
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if ((fuseidx + fusecount) > NUM_FUSES)
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return -EINVAL;
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/* init OTP */
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writel(0x01, ®s->pdstb); /* wake up from stand-by */
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writel(0x01, ®s->ptrim); /* enable repair function */
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writel(0x01, ®s->pce); /* enable input */
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/* read all requested fuses */
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for (i = 0; i < fusecount; i++, fuseidx++) {
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writel(fuseidx, ®s->pa);
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/* cycle clock to read */
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writel(0x01, ®s->pclk);
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mdelay(1);
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writel(0x00, ®s->pclk);
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mdelay(1);
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/* read the value */
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fusebuf[i] = readl(®s->pdout);
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}
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/* shut down */
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writel(0, ®s->pce);
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writel(0, ®s->ptrim);
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writel(0, ®s->pdstb);
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/* copy out */
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memcpy(buf, fusebuf, size);
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return 0;
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}
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static u32 fu540_read_serialnum(void)
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{
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int ret;
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u32 serial[2] = {0};
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for (int i = 0xfe * 4; i > 0; i -= 8) {
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ret = fu540_otp_read(i, serial, sizeof(serial));
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if (ret) {
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printf("%s: error reading from OTP\n", __func__);
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break;
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}
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if (serial[0] == ~serial[1])
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return serial[0];
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}
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return 0;
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}
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static void fu540_setup_macaddr(u32 serialnum)
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{
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/* Default MAC address */
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unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
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/*
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* We derive our board MAC address by ORing last three bytes
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* of board serial number to above default MAC address.
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*
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* This logic of deriving board MAC address is taken from
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* SiFive FSBL and is kept unchanged.
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*/
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mac[5] |= (serialnum >> 0) & 0xff;
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mac[4] |= (serialnum >> 8) & 0xff;
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mac[3] |= (serialnum >> 16) & 0xff;
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/* Update environment variable */
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eth_env_set_enetaddr("ethaddr", mac);
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}
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int misc_init_r(void)
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{
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2019-08-12 14:57:40 +00:00
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u32 serial_num;
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char buf[9] = {0};
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/* Set ethaddr environment variable from board serial number */
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if (!env_get("serial#")) {
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serial_num = fu540_read_serialnum();
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if (!serial_num) {
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WARN(true, "Board serial number should not be 0 !!\n");
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return 0;
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}
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snprintf(buf, sizeof(buf), "%08x", serial_num);
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env_set("serial#", buf);
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fu540_setup_macaddr(serial_num);
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}
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2019-06-25 06:31:44 +00:00
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return 0;
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}
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#endif
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2019-02-25 08:15:19 +00:00
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int board_init(void)
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{
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/* For now nothing to do here. */
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return 0;
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}
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