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27 lines
738 B
C
27 lines
738 B
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#define MIDR_PARTNUM_CORTEX_A35 0xD04
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#define MIDR_PARTNUM_CORTEX_A53 0xD03
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#define MIDR_PARTNUM_CORTEX_A72 0xD08
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#define MIDR_PARTNUM_SHIFT 0x4
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#define MIDR_PARTNUM_MASK (0xFFF << 0x4)
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static inline unsigned int read_midr(void)
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{
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unsigned long val;
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asm volatile("mrs %0, midr_el1" : "=r" (val));
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return val;
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}
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#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
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MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
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#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
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MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
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#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
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MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
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