u-boot/arch/arm/cpu/armv7/s5p4418/cpu.c

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arm: add support for SoC s5p4418 (cpu) / nanopi2 board Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - SPL not supported yet --> no spl-dir in arch/arm/cpu/armv7/s5p4418/. Appropriate line in Makefile removed. - cpu.c: '#include <cpu_func.h>' added. - arch/arm/cpu/armv7/s5p4418/u-boot.lds removed, is not required anylonger. - "obj-$(CONFIG_ARCH_NEXELL) += s5p-common/" added to arch/arm/cpu/armv7/Makefile since s5p-common/pwm.c is used instead of drivers/pwm/pwm-nexell.c. - s5p4418.dtsi: '#include "../../../include/generated/autoconf.h"' removed, is not necessary, error at out-of-tree building. '#ifdef CONFIG_CPU_NXP4330'-blocks (2x) removed. Some minor changes regarding mmc. 'u-boot,dm-pre-reloc' added to dp0 because of added DM_VIDEO support. - board/s5p4418/ renamed to board/friendlyarm/ - All s5p4418-boards except nanopi2 removed because there is no possibility to test the other boards. - Kconfig: Changes to have a structure like mach-bcm283x (RaspberryPi), e.g. "config ..." entries moved from/to other Kconfig. - "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. - nanopi2/board.c: All getenv(), getenv_ulong(), setenv() and saveenv() renamed to env_get(), env_get_ulong(), env_set() and env_save(), respectively. MACH_TYPE_S5P4418 is not defined anymore, therefore appropriate code removed (not necessary for DT-kernels). - nanopi2/onewire.c: All crc8() renamed to crc8_ow() because crc8() is already defined in lib/crc8.c (with different parameters). - dts: "nexell,s5pxx18-i2c" used instead of "i2c-gpio", i2c0 and i2c1 added. gmac-, ehci- and dwc2otg-entries removed because the appropriate functionality is not supported yet. New mmc-property "mmcboost" added. s5p4418-pinctrl.dtsi: gmac-entries removed, mmc- and i2c-entries added. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-10 17:07:37 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Nexell
* Hyunseok, Jung <hsjung@nexell.co.kr>
*/
#include <common.h>
#include <command.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/arch/nexell.h>
#include <asm/arch/clk.h>
#include <asm/arch/reset.h>
#include <asm/arch/tieoff.h>
#include <cpu_func.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_ARCH_CPU_INIT
#error must be define the macro "CONFIG_ARCH_CPU_INIT"
#endif
void s_init(void)
{
}
static void cpu_soc_init(void)
{
/*
* NOTE> ALIVE Power Gate must enable for Alive register access.
* must be clear wfi jump address
*/
writel(1, ALIVEPWRGATEREG);
writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
/* write 0xf0 on alive scratchpad reg for boot success check */
writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
/* set l2 cache tieoff */
nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
}
#ifdef CONFIG_PL011_SERIAL
static void serial_device_init(void)
{
char dev[10];
int id;
sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
struct clk *clk = clk_get((const char *)dev);
/* reset control: Low active ___|--- */
nx_rstcon_setrst(id, RSTCON_ASSERT);
udelay(10);
nx_rstcon_setrst(id, RSTCON_NEGATE);
udelay(10);
/* set clock */
clk_disable(clk);
clk_set_rate(clk, CONFIG_PL011_CLOCK);
clk_enable(clk);
}
#endif
int arch_cpu_init(void)
{
flush_dcache_all();
cpu_soc_init();
clk_init();
if (IS_ENABLED(CONFIG_PL011_SERIAL))
serial_device_init();
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
return 0;
}
#endif
void reset_cpu(ulong ignored)
{
void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
const u32 sw_rst_enb_bitpos = 3;
const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
const u32 sw_rst_bitpos = 12;
const u32 sw_rst_mask = 1 << sw_rst_bitpos;
int pwrcont = 0x224;
int pwrmode = 0x228;
u32 read_value;
read_value = readl((void *)(clkpwr_reg + pwrcont));
read_value &= ~sw_rst_enb_mask;
read_value |= 1 << sw_rst_enb_bitpos;
writel(read_value, (void *)(clkpwr_reg + pwrcont));
writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
}
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */