2009-09-27 16:10:09 +00:00
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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*
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* (C) Copyright 2009
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* Eric Benard <eric@eukrea.com>
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*
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* Configuration settings for the Eukrea CPU9260 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_DISPLAY_CPUINFO 1
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#define AT91_MAIN_CLOCK 18432000
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1
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#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
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#define CONFIG_CPU9260 1
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#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
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#define CONFIG_CPU9G20 1
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#endif
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_AT91SAM9G20 1
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_AT91SAM9260 1
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#else
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#error "Unknown board"
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#endif
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/* clocks */
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#if defined(CONFIG_CPU9G20)
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#define MASTER_PLL_DIV 0x01
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#define MASTER_PLL_MUL 0x2B
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#elif defined(CONFIG_CPU9260)
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#define MASTER_PLL_DIV 0x09
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#define MASTER_PLL_MUL 0x61
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#endif
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/* CKGR_MOR - enable main osc. */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_OUT | \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#endif
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_6 | \
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AT91_PMC_PDIV_2)
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#define CONFIG_SYS_MCKR2_VAL \
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CONFIG_SYS_MCKR1_VAL
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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#endif
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
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/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
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#define CONFIG_SYS_MATRIX_EBICSA_VAL \
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(AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
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AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
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/* SDRAMC_TR - Refresh Timer register */
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#define CONFIG_SYS_SDRC_TR_VAL1 0x287
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/* SDRAMC_CR - Configuration register*/
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_SDRC_CR_VAL_64MB \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(9 << 12) | /* Row Cycle Delay */ \
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(3 << 16) | /* Row Precharge Delay */ \
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(3 << 20) | /* Row to Column Delay */ \
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(6 << 24) | /* Active to Precharge Delay */ \
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(10 << 28)) /* Exit Self Refresh to Active Delay */
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#define CONFIG_SYS_SDRC_CR_VAL_128MB \
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(AT91_SDRAMC_NC_10 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(9 << 12) | /* Row Cycle Delay */ \
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(3 << 16) | /* Row Precharge Delay */ \
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(3 << 20) | /* Row to Column Delay */ \
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(6 << 24) | /* Active to Precharge Delay */ \
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(10 << 28)) /* Exit Self Refresh to Active Delay */
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_SDRC_CR_VAL_64MB \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(2 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(8 << 28)) /* Exit Self Refresh to Active Delay */
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#define CONFIG_SYS_SDRC_CR_VAL_128MB \
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(AT91_SDRAMC_NC_10 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(2 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(8 << 28)) /* Exit Self Refresh to Active Delay */
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#endif
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/* Memory Device Register -> SDRAM */
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#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit */
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
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AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
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AT91_SMC_DBW_16 | \
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AT91_SMC_TDFMODE | \
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AT91_SMC_TDF_(3))
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
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AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
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AT91_SMC_DBW_16 | \
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AT91_SMC_TDFMODE | \
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AT91_SMC_TDF_(2))
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#endif
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/* user reset enable */
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#define CONFIG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_PROCRST | \
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AT91_RSTC_RSTTYP_WAKEUP | \
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AT91_RSTC_RSTTYP_WATCHDOG)
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/* Disable Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
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AT91_WDT_WDV | \
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AT91_WDT_WDDIS | \
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AT91_WDT_WDD)
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/*
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* Hardware drivers
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*/
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#define CONFIG_ATMEL_USART 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1 /* USART 3 is DBGU */
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_BOOTP_BOOTPATH 1
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#define CONFIG_BOOTP_GATEWAY 1
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#define CONFIG_BOOTP_HOSTNAME 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_PING 1
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#define CONFIG_CMD_DHCP 1
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#define CONFIG_CMD_NAND 1
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#define CONFIG_CMD_USB 1
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#define CONFIG_CMD_FAT 1
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
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#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
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#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
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#else
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
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#endif
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/* NAND flash */
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#define CONFIG_NAND_ATMEL 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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2009-10-12 08:15:40 +00:00
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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2009-09-27 16:10:09 +00:00
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/* NOR flash */
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_2 0x12000000
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{ PHYS_FLASH_1, PHYS_FLASH_2 }
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_EMPTY_INFO 1
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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/* Ethernet */
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#define CONFIG_MACB 1
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#define CONFIG_RMII 1
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#define CONFIG_RESET_PHY_R 1
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB_SEARCH_PHY 1
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/* LEDS */
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/* Status LED */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#define CONFIG_BOARD_SPECIFIC_LED 1
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#define STATUS_LED_RED 0
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#define STATUS_LED_GREEN 1
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#define STATUS_LED_YELLOW 2
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#define STATUS_LED_BLUE 3
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/* Red */
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#define STATUS_LED_BIT STATUS_LED_RED
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#define STATUS_LED_STATE STATUS_LED_OFF
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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/* Green */
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#define STATUS_LED_BIT1 STATUS_LED_GREEN
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#define STATUS_LED_STATE1 STATUS_LED_OFF
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#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
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/* Yellow */
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#define STATUS_LED_BIT2 STATUS_LED_YELLOW
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#define STATUS_LED_STATE2 STATUS_LED_OFF
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#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
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/* Blue */
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#define STATUS_LED_BIT3 STATUS_LED_BLUE
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#define STATUS_LED_STATE3 STATUS_LED_ON
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#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
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/* Optional value */
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#define STATUS_LED_BOOT STATUS_LED_BIT
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#define CONFIG_RED_LED AT91_PIN_PC11
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#define CONFIG_GREEN_LED AT91_PIN_PC12
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#define CONFIG_YELLOW_LED AT91_PIN_PC7
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#define CONFIG_BLUE_LED AT91_PIN_PC9
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/* USB */
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#define CONFIG_USB_ATMEL 1
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_SYS_LOAD_ADDR 0x21000000
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END 0x21e00000
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#undef CONFIG_SYS_USE_NANDFLASH
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|
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#define CONFIG_SYS_USE_FLASH 1
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#if defined(CONFIG_SYS_USE_FLASH)
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|
#define CONFIG_ENV_IS_IN_FLASH 1
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|
#define CONFIG_ENV_OFFSET 0x40000
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|
#define CONFIG_ENV_SECT_SIZE 0x20000
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|
#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE 1
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|
#define CONFIG_BOOTCOMMAND "run flashboot"
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|
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
|
|
|
|
|
#define MTDPARTS_DEFAULT \
|
|
|
|
|
"mtdparts=physmap-flash.0:" \
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|
|
|
|
"256k(u-boot)ro," \
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|
|
|
"128k(u-boot-env)ro," \
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|
|
|
"1792k(kernel)," \
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|
|
|
"-(rootfs);" \
|
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|
|
"atmel_nand:-(nand)"
|
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|
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|
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|
|
#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
|
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|
|
#if defined(CONFIG_CPU9G20)
|
|
|
|
|
#define CONFIG_SYS_BASEDIR "cpu9G20"
|
|
|
|
|
#elif defined(CONFIG_CPU9260)
|
|
|
|
|
#define CONFIG_SYS_BASEDIR "cpu9260"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
|
|
"mtdids=" MTDIDS_DEFAULT "\0" \
|
|
|
|
|
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
|
|
|
|
"partition=nand0,0\0" \
|
|
|
|
|
"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
|
|
|
|
|
"ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
|
|
|
|
|
"run ramargs;bootm 22000000\0" \
|
|
|
|
|
"flashboot=run ramargs;bootm 0x10060000\0" \
|
|
|
|
|
"basedir=" CONFIG_SYS_BASEDIR "\0" \
|
|
|
|
|
"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
|
|
|
|
|
"off 0x10000000 0x1003ffff;erase 0x10000000 " \
|
|
|
|
|
"0x1003ffff;cp.b 0x24000000 0x10000000 " \
|
|
|
|
|
"$(filesize)\0" \
|
|
|
|
|
"updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
|
|
|
|
|
" 0x10060000 0x1021ffff;erase 0x10060000 " \
|
|
|
|
|
"0x1021ffff;cp.b 0x24000000 0x10060000 " \
|
|
|
|
|
"$(filesize)\0" \
|
|
|
|
|
"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
|
|
|
|
|
"protect off 0x10220000 0x13ffffff;erase " \
|
|
|
|
|
"0x10220000 0x13ffffff;cp.b 0x24000000 " \
|
|
|
|
|
"0x10220000 $(filesize)\0" \
|
|
|
|
|
""
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
|
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPU9G20)
|
|
|
|
|
#define CONFIG_SYS_PROMPT "CPU9G20=> "
|
|
|
|
|
#elif defined(CONFIG_CPU9260)
|
|
|
|
|
#define CONFIG_SYS_PROMPT "CPU9260=> "
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_CBSIZE 256
|
|
|
|
|
#define CONFIG_SYS_MAXARGS 16
|
|
|
|
|
#define CONFIG_SYS_PBSIZE \
|
|
|
|
|
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
|
|
|
#define CONFIG_SYS_LONGHELP 1
|
|
|
|
|
#define CONFIG_CMDLINE_EDITING 1
|
|
|
|
|
#define CONFIG_SILENT_CONSOLE 1
|
|
|
|
|
#define CONFIG_NETCONSOLE 1
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Size of malloc() pool
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_MALLOC_LEN \
|
|
|
|
|
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
|
|
|
|
|
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
|
|
|
|
|
|
|
|
|
#define CONFIG_STACKSIZE (32 * 1024)
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_USE_IRQ)
|
|
|
|
|
#error CONFIG_USE_IRQ not supported
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif
|
