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207 lines
5.1 KiB
C
207 lines
5.1 KiB
C
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/***************************************************************
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* Project:
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* CPLD SlaveSerial Configuration via embedded microprocessor.
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*
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* Copyright info:
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*
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* This is free software; you can redistribute it and/or modify
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* it as you like.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Description:
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*
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* This is the main source file that will allow a microprocessor
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* to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
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* and Spartan-II devices via the SlaveSerial Configuration Mode.
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* This code is discussed in Xilinx Application Note, XAPP502.
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*
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* History:
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* 3-October-2001 MN/MP - Created
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* 20-August-2008 Renesas Solutions - Modified to SH7723
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****************************************************************/
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#include <common.h>
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/* Serial */
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#define SCIF_BASE 0xffe00000 /* SCIF0 */
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#define SCSMR (vu_short *)(SCIF_BASE + 0x00)
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#define SCBRR (vu_char *)(SCIF_BASE + 0x04)
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#define SCSCR (vu_short *)(SCIF_BASE + 0x08)
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#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
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#define SC_SR (vu_short *)(SCIF_BASE + 0x10)
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
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#define RFCR (vu_long *)0xFE400020
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#define SCSCR_INIT 0x0038
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#define SCSCR_CLR 0x0000
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#define SCFCR_INIT 0x0006
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#define SCSMR_INIT 0x0080
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#define RFCR_CLR 0xA400
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#define SCI_TD_E 0x0020
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#define SCI_TDRE_CLEAR 0x00df
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#define BPS_SETTING_VALUE 1 /* 12.5MHz */
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#define WAIT_RFCR_COUNTER 500
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/* CPLD data size */
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#define CPLD_DATA_SIZE 169216
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/* out */
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#define CPLD_PFC_ADR ((vu_short *)0xA4050112)
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#define CPLD_PROG_ADR ((vu_char *)0xA4050132)
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#define CPLD_PROG_DAT 0x80
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/* in */
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#define CPLD_INIT_ADR ((vu_char *)0xA4050132)
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#define CPLD_INIT_DAT 0x40
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#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
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#define CPLD_DONE_DAT 0x20
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#define HIZCRB ((vu_short *)0xA405015A)
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/* data */
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#define CPLD_NOMAL_START 0xA0A80000
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#define CPLD_SAFE_START 0xA0AC0000
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#define MODE_SW (vu_char *)0xA405012A
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static void init_cpld_loader(void)
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{
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*SCSCR = SCSCR_CLR;
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*SCFCR = SCFCR_INIT;
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*SCSMR = SCSMR_INIT;
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*SCBRR = BPS_SETTING_VALUE;
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*RFCR = RFCR_CLR; /* Refresh counter clear */
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while (*RFCR < WAIT_RFCR_COUNTER)
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;
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*SCFCR = 0x0; /* RTRG=00, TTRG=00 */
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/* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
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*SCSCR = SCSCR_INIT;
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}
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static int check_write_ready(void)
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{
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u16 status = *SC_SR;
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return status & SCI_TD_E;
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}
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static void write_cpld_data(char ch)
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{
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while (!check_write_ready())
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;
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*SC_TDR = ch;
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*SC_SR;
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*SC_SR = SCI_TDRE_CLEAR;
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}
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static int delay(void)
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{
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int i;
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int c = 0;
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for (i = 0; i < 200; i++) {
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c = *(volatile int *)0xa0000000;
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}
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return c;
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}
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/***********************************************************************
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*
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* Function: slave_serial
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*
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* Description: Initiates SlaveSerial Configuration.
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* Calls ShiftDataOut() to output serial data
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*
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***********************************************************************/
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static void slave_serial(void)
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{
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int i;
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unsigned char *flash;
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*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
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delay();
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/*
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* Toggle Program Pin by Toggling Program_OE bit
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* This is accomplished by writing to the Program Register in the CPLD
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*
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* NOTE: The Program_OE bit should be driven high to bring the Virtex
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* Program Pin low. Likewise, it should be driven low
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* to bring the Virtex Program Pin to High-Z
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*/
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*CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
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delay();
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/*
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* Bring Program High-Z
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* (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
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*/
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/* Program_OE bit Low brings the Virtex Program Pin to High Z: */
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*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
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while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
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delay();
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/* Begin Slave-Serial Configuration */
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flash = (unsigned char *)CPLD_NOMAL_START;
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for (i = 0; i < CPLD_DATA_SIZE; i++)
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write_cpld_data(*flash++);
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}
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/***********************************************************************
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*
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* Function: check_done_bit
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*
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* Description: This function takes monitors the CPLD Input Register
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* by checking the status of the DONE bit in that Register.
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* By doing so, it monitors the Xilinx Virtex device's DONE
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* Pin to see if configuration bitstream has been properly
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* loaded
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*
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***********************************************************************/
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static void check_done_bit(void)
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{
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while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
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;
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}
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/***********************************************************************
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*
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* Function: init_cpld
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*
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* Description: Begins Slave Serial configuration of Xilinx FPGA
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*
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***********************************************************************/
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void init_cpld(void)
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{
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/* Init serial device */
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init_cpld_loader();
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if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
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return;
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*HIZCRB = 0x0000;
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*CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
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/* write CPLD data from NOR flash to device */
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slave_serial();
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/*
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* Monitor the DONE bit in the CPLD Input Register to see if
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* configuration successful
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*/
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check_done_bit();
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}
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