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u-boot/arch/x86/dts/link.dts

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x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
/dts-v1/;
dt: don't use ARCH_CPU_DTS Now that we assume dtc supports the -i option, we don't need to use ARCH_CPU_DTS in *.dts{,i}; we simply specify the include filename directly, and dtc will find it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2013-07-24 17:09:20 +00:00
/include/ "coreboot.dtsi"
x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
/ {
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
#address-cells = <1>;
#size-cells = <1>;
x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
config {
silent_console = <0>;
};
dm: x86: dts: Add additional info to the serial port node Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:49:19 +00:00
gpioa {
compatible = "intel,ich6-gpio";
x86: chromebook_link: Enable GPIO support Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:25 +00:00
u-boot,dm-pre-reloc;
dm: x86: dts: Add additional info to the serial port node Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:49:19 +00:00
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
x86: chromebook_link: Enable GPIO support Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:25 +00:00
u-boot,dm-pre-reloc;
dm: x86: dts: Add additional info to the serial port node Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:49:19 +00:00
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
x86: chromebook_link: Enable GPIO support Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:25 +00:00
u-boot,dm-pre-reloc;
dm: x86: dts: Add additional info to the serial port node Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:49:19 +00:00
reg = <0x40 0x10>;
bank-name = "C";
};
x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
x86: Add FDT SPI node for link Add a memory-mapped 8GB SPI chip. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-11 06:08:10 +00:00
x86: ivybridge: Implement SDRAM init Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:28 +00:00
spd {
compatible = "memory-spd";
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
reg = <0>;
data = [92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 81
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 42 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 02 fe 00
11 52 00 00 00 07 7f 37
45 42 4a 32 30 55 47 36
45 42 55 30 2d 47 4e 2d
46 20 30 20 02 fe 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
samsung_4Gb_1600_1.35v_x16 {
reg = <1>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
f0 0a 3c 3c 01 40 83 01
00 80 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 ce 01
00 00 00 00 00 00 6a 04
4d 34 37 31 42 35 36 37
34 42 48 30 2d 59 4b 30
20 20 00 00 80 ce 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
micron_4Gb_1600_1.35v_x16 {
reg = <2>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 05
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 01 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 2c 00
00 00 00 00 00 00 ad 75
34 4b 54 46 32 35 36 36
34 48 5a 2d 31 47 36 45
31 20 45 31 80 2c 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff];
};
};
x86: Add FDT SPI node for link Add a memory-mapped 8GB SPI chip. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-11 06:08:10 +00:00
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9";
spi-flash@0 {
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
memory-map = <0xff800000 0x00800000>;
};
};
x86: Add device tree information for Chrome OS EC Add the required node describing how to find the EC on link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:30:13 +00:00
x86: dts: Move PCI peripherals into a pci node These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 01:18:36 +00:00
pci {
x86: dts: Add SATA settings for link Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 01:18:39 +00:00
sata {
compatible = "intel,pantherpoint-ahci";
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x00880a7f>;
};
x86: dts: Add video information to the device tree This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 03:56:37 +00:00
gma {
compatible = "intel,gma";
intel,dp_hotplug = <0 0 0x06>;
intel,panel-port-select = <1>;
intel,panel-power-cycle-delay = <6>;
intel,panel-power-up-delay = <2000>;
intel,panel-power-down-delay = <500>;
intel,panel-power-backlight-on-delay = <2000>;
intel,panel-power-backlight-off-delay = <2000>;
intel,cpu-backlight = <0x00000200>;
intel,pch-backlight = <0x04000000>;
};
x86: dts: Move PCI peripherals into a pci node These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 01:18:36 +00:00
lpc {
compatible = "intel,lpc";
x86: Add device tree information for Chrome OS EC Add the required node describing how to find the EC on link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:30:13 +00:00
#address-cells = <1>;
#size-cells = <1>;
x86: dts: Move PCI peripherals into a pci node These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 01:18:36 +00:00
gen-dec = <0x800 0xfc 0x900 0xfc>;
x86: dts: Add LPC settings for link Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 01:18:37 +00:00
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
0x80 0x80 0x80 0x80>;
intel,gpi-routing = <0 0 0 0 0 0 0 2
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
x86: dts: Move PCI peripherals into a pci node These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-15 01:18:36 +00:00
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
/* Describes the flash memory within the EC */
#address-cells = <1>;
#size-cells = <1>;
flash@8000000 {
reg = <0x08000000 0x20000>;
erase-value = <0xff>;
};
x86: Add device tree information for Chrome OS EC Add the required node describing how to find the EC on link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:30:13 +00:00
};
};
};
x86: dts: Add microcode updates for ivybridge CPU Add two microcode updates that are provided for this CPU. The updates have been converted to a device tree form. Note: SPDX submission has been done. If this license is approved I will convert the files to use SPDX. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:22 +00:00
microcode {
update@0 {
#include "m12206a7_00000028.dtsi"
};
update@1 {
#include "m12306a9_00000017.dtsi"
};
};
x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
};
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