u-boot/board/dhelectronics/dh_imx8mp/lpddr4_timing.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2022 Marek Vasut <marex@denx.de>
 */

#ifndef __LPDDR4_TIMING_H__
#define __LPDDR4_TIMING_H__

extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;

typedef void (*scrub_func_t)(void);
extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);

u8 dh_get_memcfg(void);

#define DDRC_ECCCFG0_ECC_MODE_MASK	0x7

#endif /* __LPDDR4_TIMING_H__ */
ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2 Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, SPI NOR and USB 3.0 host. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> 2022-05-21 14:56:26 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
			`/*`
			`* Copyright 2022 Marek Vasut <marex@denx.de>`
			`*/`

			`#ifndef __LPDDR4_TIMING_H__`
			`#define __LPDDR4_TIMING_H__`

ARM: imx: Add 2 GiB DRAM support for DH electronics i.MX8M Plus DHCOM The DH electronics i.MX8M Plus DHCOM SoM currently supports only 4 GiB of DRAM population option. Add another population option with 2 GiB of DRAM. The chips used on the 2 GiB option are 2x K4F6E3S4HM-MGCJ . Signed-off-by: Marek Vasut <marex@denx.de> 2023-02-11 21:49:01 +00:00			`extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;`
ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2 Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, SPI NOR and USB 3.0 host. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> 2022-05-21 14:56:26 +00:00			`extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;`

ARM: imx: Update DRAM timings with inline ECC on DH i.MX8MP DHCOM SoM Import DRAM timings generated by the DDR tool 3.31 which introduce assorted tweaks to the DRAM controller settings. Furthermore, enable DBI to improve noise resilience of the DRAM bus by reducing the number of bit changes on the bus. Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors reported by EDAC . It is not entirely clear why the slightly faster setting does produce sporadic correctable errors, while this one does not, but this could be related to simpler PLL setting at 3600 MTps. Enable inline ECC which is necessary to detect ECC errors and collect statistics by the EDAC driver in Linux. This reduces the DRAM size by 64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size becomes 1.8 GiB. Signed-off-by: Marek Vasut <marex@denx.de> 2023-12-16 05:42:29 +00:00			`typedef void (*scrub_func_t)(void);`
			`extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);`
			`extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);`

ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2 Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, SPI NOR and USB 3.0 host. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> 2022-05-21 14:56:26 +00:00			`u8 dh_get_memcfg(void);`

ARM: imx: Update DRAM timings with inline ECC on DH i.MX8MP DHCOM SoM Import DRAM timings generated by the DDR tool 3.31 which introduce assorted tweaks to the DRAM controller settings. Furthermore, enable DBI to improve noise resilience of the DRAM bus by reducing the number of bit changes on the bus. Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors reported by EDAC . It is not entirely clear why the slightly faster setting does produce sporadic correctable errors, while this one does not, but this could be related to simpler PLL setting at 3600 MTps. Enable inline ECC which is necessary to detect ECC errors and collect statistics by the EDAC driver in Linux. This reduces the DRAM size by 64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size becomes 1.8 GiB. Signed-off-by: Marek Vasut <marex@denx.de> 2023-12-16 05:42:29 +00:00			`#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7`

ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2 Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, SPI NOR and USB 3.0 host. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> 2022-05-21 14:56:26 +00:00			`#endif /* __LPDDR4_TIMING_H__ */`