2018-05-06 21:58:06 +00:00
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# SPDX-License-Identifier: GPL-2.0+
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2012-10-04 06:46:02 +00:00
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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2017-04-25 18:44:48 +00:00
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# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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2012-10-04 06:46:02 +00:00
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2017-04-25 18:44:48 +00:00
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obj-y += board.o
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obj-y += clock_manager.o
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obj-y += misc.o
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2015-12-02 19:31:32 +00:00
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2017-04-25 18:44:48 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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obj-y += clock_manager_gen5.o
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obj-y += misc_gen5.o
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obj-y += reset_manager_gen5.o
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obj-y += scan_manager.o
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obj-y += system_manager_gen5.o
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2018-05-23 16:17:29 +00:00
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obj-y += timer.o
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2017-04-25 18:44:48 +00:00
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obj-y += wrap_pll_config.o
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2017-07-26 05:05:38 +00:00
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obj-y += fpga_manager.o
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2017-04-25 18:44:48 +00:00
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endif
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2017-04-25 18:44:38 +00:00
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2017-04-25 18:44:48 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += clock_manager_arria10.o
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obj-y += misc_arria10.o
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obj-y += pinmux_arria10.o
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obj-y += reset_manager_arria10.o
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endif
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2015-08-02 19:12:09 +00:00
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2018-05-18 14:05:22 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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obj-y += clock_manager_s10.o
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2020-12-24 10:20:58 +00:00
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obj-y += lowlevel_init_soc64.o
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2018-05-23 16:17:25 +00:00
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obj-y += mailbox_s10.o
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2018-05-23 16:17:24 +00:00
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obj-y += misc_s10.o
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2018-05-23 16:17:26 +00:00
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obj-y += mmu-arm64_s10.o
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2018-05-18 14:05:23 +00:00
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obj-y += reset_manager_s10.o
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2018-05-18 14:05:24 +00:00
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obj-y += system_manager_s10.o
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2018-05-23 16:17:29 +00:00
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obj-y += timer_s10.o
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2018-05-18 14:05:24 +00:00
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obj-y += wrap_pinmux_config_s10.o
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2018-05-18 14:05:22 +00:00
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obj-y += wrap_pll_config_s10.o
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endif
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2018-05-23 16:17:28 +00:00
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2019-11-27 07:55:23 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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obj-y += clock_manager_agilex.o
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2020-12-24 10:20:58 +00:00
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obj-y += lowlevel_init_soc64.o
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2019-11-27 07:55:32 +00:00
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obj-y += mailbox_s10.o
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obj-y += misc_s10.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-y += system_manager_s10.o
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obj-y += timer_s10.o
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obj-y += wrap_pinmux_config_s10.o
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obj-y += wrap_pll_config_s10.o
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2019-11-27 07:55:23 +00:00
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endif
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2017-04-25 18:44:48 +00:00
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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2018-05-23 16:17:27 +00:00
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obj-y += spl_gen5.o
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2017-04-25 18:44:48 +00:00
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obj-y += freeze_controller.o
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obj-y += wrap_iocsr_config.o
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obj-y += wrap_pinmux_config.o
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obj-y += wrap_sdram_config.o
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endif
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2018-05-23 16:17:27 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += spl_a10.o
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endif
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2018-05-23 16:17:28 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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2019-11-27 07:55:15 +00:00
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obj-y += firewall.o
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2018-05-23 16:17:28 +00:00
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obj-y += spl_s10.o
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endif
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2019-11-27 07:55:29 +00:00
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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2019-11-27 07:55:32 +00:00
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obj-y += firewall.o
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2019-11-27 07:55:29 +00:00
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obj-y += spl_agilex.o
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endif
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2020-12-24 10:21:00 +00:00
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else
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obj-$(CONFIG_SPL_ATF) += smc_api.o
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2017-04-25 18:44:48 +00:00
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endif
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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2015-08-02 19:12:09 +00:00
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# QTS-generated config file wrappers
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CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
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2017-04-25 18:44:48 +00:00
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endif
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