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u-boot/drivers/clk/Makefile

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dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
#
# Copyright (c) 2015 Google, Inc
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
spl: dm: Kconfig: split CLK support for SPL and TPL Introduce TPL_CLK to allow finer-grained selection of TPL features for feature-rich (i.e. DM-based) TPL stages. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-28 23:45:01 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
clock: add Tegra186 clock driver In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 17:28:24 +00:00
obj-y += tegra/
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
clk: add Amlogic meson clock driver Introduce a basic clock driver for Amlogic Meson SoCs which supports enabling/disabling clock gates and getting their frequency. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-14 11:43:39 +00:00
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
clk: socfpga: Add initial Arria10 clock driver Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-31 15:58:07 +00:00
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
obj-$(CONFIG_CLK_AT91) += at91/
driver: clk: Add support for clocks on Armada 37xx The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-04-24 15:21:25 +00:00
obj-$(CONFIG_CLK_MVEBU) += mvebu/
dm: clk: add BCM6345 clock driver This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-07 18:13:01 +00:00
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
clk: boston: Providea simple driver for Boston board clocks Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-08 06:47:38 +00:00
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_EXYNOS) += exynos/
ARC: clk: introduce HSDK CGU clock driver Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-10 18:20:08 +00:00
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
clk: Add Actions Semi OWL clock support This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-14 18:08:35 +00:00
obj-$(CONFIG_CLK_OWL) += owl/
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_RENESAS) += renesas/
clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs rename it to a more generic clk_stm32f.c Fix also some checkpatch errors/warnings. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-15 12:14:48 +00:00
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
clk: add driver for stm32mp1 add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-12 09:46:15 +00:00
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
clk: Add ICS8N3QV01 driver Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-04-27 12:53:15 +00:00
obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
dm: clk: add clk driver support for stm32h7 SoCs This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:06 +00:00
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
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