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u-boot/configs/socfpga_agilex_defconfig

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arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x1000
CONFIG_SYS_MALLOC_F_LEN=0x2000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-10 19:31:07 +00:00
CONFIG_NR_DRAM_BANKS=2
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-11-30 17:50:32 +00:00
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x3fe00000
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-28 20:15:47 +00:00
CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-22 18:38:00 +00:00
CONFIG_DM_GPIO=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-06 17:54:25 +00:00
CONFIG_SPL_TEXT_BASE=0xFFE00000
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET Don't invoke 'SYSTEM_RESET' PSCI function because PSCI function calls are not supported by u-boot running in EL3. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-08-14 03:07:23 +00:00
# CONFIG_PSCI_RESET is not set
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-29 14:48:01 +00:00
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
CONFIG_BOOTDELAY=5
Convert CONFIG_BOOTARGS to Kconfig This converts the following to Kconfig: CONFIG_BOOTARGS Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-16 23:06:12 +00:00
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to *_defconfig file for both Stratix 10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-01 12:04:14 +00:00
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_DM_RESET=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
arm: socfpga: Use DM watchdog timer All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-08-06 04:15:33 +00:00
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
# CONFIG_SPL_USE_TINY_PRINTF is not set
configs: socfpga: soc64: Avoid SPL enter infinite loop during exception In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-08-05 10:34:33 +00:00
CONFIG_PANIC_HANG=y
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