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u-boot/arch/arm/mach-stm32mp/Makefile

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stm32mp1: add bsec driver Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-17 13:24:05 +00:00
# SPDX-License-Identifier: GPL-2.0+
arm: stm32: add new architecture for STM32MP family - add new arch stm32mp for STM32 MPU/Soc based on Cortex A - support for stm32mp157 SOC - SPL is used as first boot stage loader - using driver model for all the drivers, even in SPL - all security feature are deactivated (ETZC and TZC) - reused STM32 MCU drivers when it is possible Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-12 09:46:10 +00:00
#
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
obj-y += cpu.o
obj-y += dram_init.o
stm32mp: add syscon for STGEN Add STGEN as SYSCON device: allow access to device address defined in device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-20 10:45:14 +00:00
obj-y += syscon.o
arm: stm32mp: spl: add bsec driver in SPL Add the bsec driver in SPL, as it is needed by SOC part number detection to found the supported OPP. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-25 10:19:41 +00:00
obj-y += bsec.o
arm: stm32: add new architecture for STM32MP family - add new arch stm32mp for STM32 MPU/Soc based on Cortex A - support for stm32mp157 SOC - SPL is used as first boot stage loader - using driver model for all the drivers, even in SPL - all security feature are deactivated (ETZC and TZC) - reused STM32 MCU drivers when it is possible Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-12 09:46:10 +00:00
stm32mp1: add bsec driver Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-17 13:24:05 +00:00
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
stm32mp: add the command stm32prog Add a specific command stm32prog for STM32MP soc family witch allows to program the boot devices with the tool STM32CubeProgrammer (http://www.st.com/STM32CubeProg). This command uses the same UART STM32 protocol than MCU STM32 with or USB with DFU protocol v1.1 (ithe MCU ST extension are no supported). The executed actions are based on a tab separated value file with a stm32 header, the FlashLayout file (https://wiki.st.com/stm32mpu/wiki/STM32CubeProgrammer_flashlayout). This file is parsed by the U-Boot command to: - initialize the devices - create the partition table on each device - initialize the DFU backend to access to not volatile memory (NOR/NAND/SD/eMMC) or to virtual device (OTP/PMIC) Up to STM32PROG_MAX_DEV (5) devices can be updated with a FlashLayout. The communication between U-Boot and STM32CubeProgrammer is done with the specific alternate configuration (see "AN5275: USB DFU/USART protocols used in STM32MP1 Series bootloaders" for details). The command stm32prog is executed when a boot from USB is detected (selected with bootpins) and we can program the boot devices with a simple command (on Windows or Linux): PC $> STM32_Programmer_CLI -c port=usb1 -w flaslayout.tsv 1/ the ROM code loads TF-A in embedded RAM (DFU or uart) 2/ TF-A loads flashlayout file and U-Boot in DDR (DFU or uart) 3/ U-Boot executes the stm32prog command (DFU or uart) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-18 08:24:49 +00:00
obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/
stm32mp1: key: add stm32key command Add dedicated command to register in fuse a public hash key provided by keygen tool. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-05 15:20:17 +00:00
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
arm: stm32mp1: add PSCI support Add PSCI v1.0 support for Linux and manage PSCI state for each CPU (affinity 0 level) with all mandatory functions: - PSCI_VERSION - CPU_SUSPEND - CPU_OFF - CPU_ON - AFFINITY_INFO - SYSTEM_OFF - SYSTEM_RESET - PSCI_FEATURES and 1 optional to avoid Linux warning - MIGRATE_INFO_TYPE Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
2018-04-16 08:13:24 +00:00
obj-$(CONFIG_ARMV7_PSCI) += psci.o
board: stm32mp1: use FDT address provided by TF-A at boot time Save and use the FDT address provided by TF-A in r2 at boot time (it is NT_FW_CONFIG = Non Trusted Firmware configuration file) Address is saved in save_boot_params(), called by start.S and the used DTB is gd->fdt_blob = board_fdt_blob_setup(). If dtb is not provided or invalid, U-Boot use as fallback the builtin DTB. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-18 08:22:50 +00:00
obj-$(CONFIG_TFABOOT) += boot_params.o
stm32mp1: Makefile cleanup Don't compile psci for SPL build. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-30 17:16:53 +00:00
endif
stm32mp: regulator: add SoC pwr regulator support This driver binds and manages the following regulator of SoC's PWR block : - reg11 - reg18 - usb33 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-26 14:45:18 +00:00
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
stm32mp1: update package information in device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-05 15:20:14 +00:00
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
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