2017-06-01 10:00:36 +00:00
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RV1108_H
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#define _ASM_ARCH_CRU_RV1108_H
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#include <common.h>
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (600 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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struct rv1108_clk_priv {
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struct rv1108_cru *cru;
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ulong rate;
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};
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struct rv1108_cru {
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struct rv1108_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int con5;
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unsigned int reserved[2];
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} pll[3];
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unsigned int clksel_con[46];
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unsigned int reserved1[2];
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unsigned int clkgate_con[20];
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unsigned int reserved2[4];
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unsigned int softrst_con[13];
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unsigned int reserved3[3];
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unsigned int glb_srst_fst_val;
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unsigned int glb_srst_snd_val;
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unsigned int glb_cnt_th;
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unsigned int misc_con;
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unsigned int glb_rst_con;
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unsigned int glb_rst_st;
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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};
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check_member(rv1108_cru, emmc_con[1], 0x01ec);
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struct pll_div {
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u32 refdiv;
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u32 fbdiv;
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u32 postdiv1;
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u32 postdiv2;
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u32 frac;
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};
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enum {
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/* PLL CON0 */
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FBDIV_MASK = 0xfff,
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FBDIV_SHIFT = 0,
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/* PLL CON1 */
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POSTDIV2_SHIFT = 12,
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POSTDIV2_MASK = 7 << POSTDIV2_SHIFT,
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POSTDIV1_SHIFT = 8,
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POSTDIV1_MASK = 7 << POSTDIV1_SHIFT,
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REFDIV_MASK = 0x3f,
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REFDIV_SHIFT = 0,
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/* PLL CON2 */
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LOCK_STA_SHIFT = 31,
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LOCK_STA_MASK = 1 << LOCK_STA_SHIFT,
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FRACDIV_MASK = 0xffffff,
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FRACDIV_SHIFT = 0,
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/* PLL CON3 */
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WORK_MODE_SHIFT = 8,
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WORK_MODE_MASK = 1 << WORK_MODE_SHIFT,
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WORK_MODE_SLOW = 0,
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WORK_MODE_NORMAL = 1,
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DSMPD_SHIFT = 3,
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DSMPD_MASK = 1 << DSMPD_SHIFT,
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/* CLKSEL0_CON */
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CORE_PLL_SEL_SHIFT = 8,
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CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT,
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CORE_PLL_SEL_APLL = 0,
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CORE_PLL_SEL_GPLL = 1,
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CORE_PLL_SEL_DPLL = 2,
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CORE_CLK_DIV_SHIFT = 0,
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CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
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2017-09-20 06:28:18 +00:00
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/* CLKSEL_CON22 */
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CLK_SARADC_DIV_CON_SHIFT= 0,
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CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
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CLK_SARADC_DIV_CON_WIDTH= 10,
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2017-06-01 10:00:36 +00:00
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/* CLKSEL24_CON */
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MAC_PLL_SEL_SHIFT = 12,
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MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
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MAC_PLL_SEL_APLL = 0,
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MAC_PLL_SEL_GPLL = 1,
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RMII_EXTCLK_SEL_SHIFT = 8,
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
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MAC_CLK_DIV_MASK = 0x1f,
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MAC_CLK_DIV_SHIFT = 0,
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/* CLKSEL27_CON */
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SFC_PLL_SEL_SHIFT = 7,
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SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
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SFC_PLL_SEL_DPLL = 0,
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SFC_PLL_SEL_GPLL = 1,
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SFC_CLK_DIV_SHIFT = 0,
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SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT,
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};
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#endif
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