u-boot/arch/arm/mach-rockchip/rk3036/Makefile

#
# (C) Copyright 2015 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier:     GPL-2.0+
#

obj-y += clk_rk3036.o

ifndef CONFIG_SPL_BUILD
obj-y += syscon_rk3036.o
endif

obj-y += sdram_rk3036.o
rockchip: rk3036: Add Soc reset driver We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:18 +00:00			`#`
			`# (C) Copyright 2015 Rockchip Electronics Co., Ltd`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

rockchip: rk3036: Move rockchip_get_cru() out of the driver This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 2016-10-02 02:04:50 +00:00			`obj-y += clk_rk3036.o`

rockchip: rk3036: Add Soc reset driver We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:18 +00:00			`ifndef CONFIG_SPL_BUILD`
rockchip: rk3036: Add a simple syscon driver Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:19 +00:00			`obj-y += syscon_rk3036.o`
rockchip: rk3036: Add Soc reset driver We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:18 +00:00			`endif`
rockchip: add rk3036 sdram driver add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2015-11-17 06:20:26 +00:00
			`obj-y += sdram_rk3036.o`