2018-05-06 21:58:06 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2007-07-06 03:39:07 +00:00
|
|
|
/*
|
|
|
|
* ColdFire Internal Memory Map and Defines
|
|
|
|
*
|
2012-10-18 19:25:51 +00:00
|
|
|
* Copyright 2004-2012 Freescale Semiconductor, Inc.
|
2007-07-06 03:39:07 +00:00
|
|
|
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __IMMAP_H
|
|
|
|
#define __IMMAP_H
|
2007-07-16 11:11:12 +00:00
|
|
|
|
2009-06-12 11:29:00 +00:00
|
|
|
#if defined(CONFIG_MCF520x)
|
|
|
|
#include <asm/immap_520x.h>
|
|
|
|
#include <asm/m520x.h>
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
|
2009-06-12 11:29:00 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (6)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
|
|
|
#endif /* CONFIG_M520x */
|
|
|
|
|
2007-08-17 00:23:50 +00:00
|
|
|
#ifdef CONFIG_M5235
|
|
|
|
#include <asm/immap_5235.h>
|
|
|
|
#include <asm/m5235.h>
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2007-08-17 00:23:50 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
2007-08-17 00:23:50 +00:00
|
|
|
#endif
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
2007-08-17 00:23:50 +00:00
|
|
|
#endif /* CONFIG_M5235 */
|
|
|
|
|
2007-08-16 00:38:15 +00:00
|
|
|
#ifdef CONFIG_M5249
|
|
|
|
#include <asm/immap_5249.h>
|
|
|
|
#include <asm/m5249.h>
|
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2007-08-16 00:38:15 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (64)
|
2007-08-16 00:38:15 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (31)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
|
2007-08-16 00:38:15 +00:00
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M5249 */
|
|
|
|
|
2007-08-16 18:20:50 +00:00
|
|
|
#ifdef CONFIG_M5253
|
|
|
|
#include <asm/immap_5253.h>
|
|
|
|
#include <asm/m5249.h>
|
|
|
|
#include <asm/m5253.h>
|
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2007-08-16 18:20:50 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (64)
|
2007-08-16 18:20:50 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (27)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
|
2007-08-16 18:20:50 +00:00
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M5253 */
|
|
|
|
|
2007-08-16 00:38:15 +00:00
|
|
|
#ifdef CONFIG_M5271
|
|
|
|
#include <asm/immap_5271.h>
|
|
|
|
#include <asm/m5271.h>
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2007-08-16 00:38:15 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
2009-03-26 19:26:01 +00:00
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
2007-08-16 00:38:15 +00:00
|
|
|
#endif
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
2007-08-16 00:38:15 +00:00
|
|
|
#endif /* CONFIG_M5271 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_M5272
|
|
|
|
#include <asm/immap_5272.h>
|
|
|
|
#include <asm/m5272.h>
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2007-08-16 00:38:15 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (64)
|
2007-08-16 00:38:15 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
2007-08-16 00:38:15 +00:00
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M5272 */
|
|
|
|
|
2008-02-04 21:38:20 +00:00
|
|
|
#ifdef CONFIG_M5275
|
|
|
|
#include <asm/immap_5275.h>
|
|
|
|
#include <asm/m5275.h>
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
|
|
|
|
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2008-02-04 21:38:20 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (192)
|
2008-02-04 21:38:20 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
2008-02-04 21:38:20 +00:00
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M5275 */
|
|
|
|
|
2007-08-16 00:38:15 +00:00
|
|
|
#ifdef CONFIG_M5282
|
|
|
|
#include <asm/immap_5282.h>
|
|
|
|
#include <asm/m5282.h>
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
|
2007-08-16 00:38:15 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
2007-08-16 00:38:15 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
2007-08-16 00:38:15 +00:00
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M5282 */
|
|
|
|
|
2015-02-12 00:40:00 +00:00
|
|
|
#ifdef CONFIG_M5307
|
|
|
|
#include <asm/immap_5307.h>
|
|
|
|
#include <asm/m5307.h>
|
|
|
|
|
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
|
2022-11-16 18:10:41 +00:00
|
|
|
(CFG_SYS_UART_PORT * 0x40))
|
2015-02-12 00:40:00 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (64)
|
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
|
|
|
|
(CONFIG_SYS_INTR_BASE))->ipr)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (31)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
|
|
|
|
MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M5307 */
|
|
|
|
|
2008-10-22 11:38:21 +00:00
|
|
|
#if defined(CONFIG_MCF5301x)
|
|
|
|
#include <asm/immap_5301x.h>
|
|
|
|
#include <asm/m5301x.h>
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
|
|
|
|
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
|
2008-10-22 11:38:21 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (6)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
|
|
|
#endif /* CONFIG_M5301x */
|
|
|
|
|
2008-01-14 23:23:08 +00:00
|
|
|
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
|
2007-07-06 03:39:07 +00:00
|
|
|
#include <asm/immap_5329.h>
|
|
|
|
#include <asm/m5329.h>
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
|
2007-07-06 03:39:07 +00:00
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (6)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
2007-07-06 03:39:07 +00:00
|
|
|
#endif
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
2008-01-14 23:23:08 +00:00
|
|
|
#endif /* CONFIG_M5329 && CONFIG_M5373 */
|
2007-07-16 11:11:12 +00:00
|
|
|
|
2012-10-18 19:25:51 +00:00
|
|
|
#if defined(CONFIG_M54418)
|
|
|
|
#include <asm/immap_5441x.h>
|
|
|
|
#include <asm/m5441x.h>
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
|
|
|
|
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
|
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#if (CFG_SYS_UART_PORT < 4)
|
2012-10-18 19:25:51 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
|
2022-11-16 18:10:41 +00:00
|
|
|
(CFG_SYS_UART_PORT * 0x4000))
|
2012-10-18 19:25:51 +00:00
|
|
|
#else
|
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
|
2022-11-16 18:10:41 +00:00
|
|
|
((CFG_SYS_UART_PORT - 4) * 0x4000))
|
2012-10-18 19:25:51 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#define MMAP_DSPI MMAP_DSPI0
|
|
|
|
|
|
|
|
/* Timer */
|
|
|
|
#ifdef CONFIG_MCFTMR
|
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (6)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
2018-02-04 20:13:12 +00:00
|
|
|
#define CONFIG_SYS_NUM_IRQS (192)
|
2012-10-18 19:25:51 +00:00
|
|
|
|
|
|
|
#endif /* CONFIG_M54418 */
|
|
|
|
|
2008-01-15 19:39:44 +00:00
|
|
|
#ifdef CONFIG_M547x
|
|
|
|
#include <asm/immap_547x_8x.h>
|
|
|
|
#include <asm/m547x_8x.h>
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSLDMAFEC
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
|
|
|
|
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
|
2008-01-15 19:39:44 +00:00
|
|
|
|
|
|
|
#define FEC0_RX_TASK 0
|
|
|
|
#define FEC0_TX_TASK 1
|
|
|
|
#define FEC0_RX_PRIORITY 6
|
|
|
|
#define FEC0_TX_PRIORITY 7
|
|
|
|
#define FEC0_RX_INIT 16
|
|
|
|
#define FEC0_TX_INIT 17
|
|
|
|
#define FEC1_RX_TASK 2
|
|
|
|
#define FEC1_TX_TASK 3
|
|
|
|
#define FEC1_RX_PRIORITY 6
|
|
|
|
#define FEC1_TX_PRIORITY 7
|
|
|
|
#define FEC1_RX_INIT 30
|
|
|
|
#define FEC1_TX_INIT 31
|
|
|
|
#endif
|
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
|
2008-01-15 19:39:44 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_SLTTMR
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
|
|
|
|
#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
|
|
|
|
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
|
|
|
|
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
|
|
|
|
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
|
|
|
|
#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
|
2008-01-15 19:39:44 +00:00
|
|
|
#endif
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
|
|
|
|
#define CONFIG_SYS_NUM_IRQS (128)
|
2008-01-15 19:39:44 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
2022-11-16 18:10:33 +00:00
|
|
|
#define CFG_SYS_PCI_BAR0 (0x40000000)
|
2022-11-16 18:10:37 +00:00
|
|
|
#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
|
2022-11-16 18:10:37 +00:00
|
|
|
#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
|
2008-01-15 19:39:44 +00:00
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_M547x */
|
|
|
|
|
2007-07-06 03:39:07 +00:00
|
|
|
#endif /* __IMMAP_H */
|