2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-10-23 23:58:20 +00:00
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
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*/
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#include <common.h>
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#include <asm/io.h>
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2019-08-01 15:46:52 +00:00
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#include <env.h>
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2016-09-21 02:28:55 +00:00
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#include <linux/errno.h>
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2011-10-23 23:58:20 +00:00
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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2013-05-03 10:32:20 +00:00
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#include <asm/arch/iomux-mx35.h>
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2011-10-23 23:58:20 +00:00
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#include <i2c.h>
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#include <linux/types.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <netdev.h>
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2016-10-17 13:51:32 +00:00
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#include <fdt_support.h>
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#include <mtd_node.h>
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#include <jffs2/load_kernel.h>
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2011-10-23 23:58:20 +00:00
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#ifndef CONFIG_BOARD_EARLY_INIT_F
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#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
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#endif
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#define CCM_CCMR_CONFIG 0x003F4208
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#define ESDCTL_DDR2_CONFIG 0x007FFC3F
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static inline void dram_wait(unsigned int count)
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{
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volatile unsigned int wait = count;
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while (wait--)
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;
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}
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void board_setup_sdram(void)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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/* Initialize with default values both CSD0/1 */
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writel(0x2000, &esdc->esdctl0);
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writel(0x2000, &esdc->esdctl1);
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2016-10-17 13:51:33 +00:00
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mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
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13, 10, 2, 0x8080);
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2011-10-23 23:58:20 +00:00
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}
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static void setup_iomux_uart3(void)
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{
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2013-05-03 10:32:20 +00:00
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static const iomux_v3_cfg_t uart3_pads[] = {
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MX35_PAD_RTS2__UART3_RXD_MUX,
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MX35_PAD_CTS2__UART3_TXD_MUX,
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};
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imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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2011-10-23 23:58:20 +00:00
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}
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2013-05-03 10:32:20 +00:00
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#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
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2011-10-23 23:58:20 +00:00
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c_pads[] = {
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NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
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2011-10-23 23:58:20 +00:00
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2013-05-03 10:32:20 +00:00
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NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
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};
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2011-10-23 23:58:20 +00:00
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2013-05-03 10:32:20 +00:00
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imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
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2011-10-23 23:58:20 +00:00
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}
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static void setup_iomux_spi(void)
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{
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static const iomux_v3_cfg_t spi_pads[] = {
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MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
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MX35_PAD_CSPI1_MISO__CSPI1_MISO,
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MX35_PAD_CSPI1_SS0__CSPI1_SS0,
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MX35_PAD_CSPI1_SS1__CSPI1_SS1,
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MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
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};
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
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2011-10-23 23:58:20 +00:00
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}
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static void setup_iomux_fec(void)
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{
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2013-05-03 10:32:20 +00:00
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static const iomux_v3_cfg_t fec_pads[] = {
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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2016-10-17 13:51:34 +00:00
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/* GPIO used to power off ethernet */
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MX35_PAD_STXFS4__GPIO2_31,
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2013-05-03 10:32:20 +00:00
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};
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2011-10-23 23:58:20 +00:00
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2013-05-03 10:32:20 +00:00
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/* setup pins for FEC */
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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2011-10-23 23:58:20 +00:00
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}
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int board_early_init_f(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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/* setup GPIO3_1 to set HighVCore signal */
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2013-05-03 10:32:20 +00:00
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imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
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2011-10-23 23:58:20 +00:00
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gpio_direction_output(65, 1);
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/* initialize PLL and clock configuration */
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writel(CCM_CCMR_CONFIG, &ccm->ccmr);
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writel(CCM_MPLL_532_HZ, &ccm->mpctl);
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writel(CCM_PPLL_300_HZ, &ccm->ppctl);
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/* Set the core to run at 532 Mhz */
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writel(0x00001000, &ccm->pdr0);
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/* Set-up RAM */
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board_setup_sdram();
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/* enable clocks */
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writel(readl(&ccm->cgr0) |
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MXC_CCM_CGR0_EMI_MASK |
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2012-08-14 03:28:24 +00:00
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MXC_CCM_CGR0_EDIO_MASK |
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2011-10-23 23:58:20 +00:00
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MXC_CCM_CGR0_EPIT1_MASK,
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&ccm->cgr0);
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writel(readl(&ccm->cgr1) |
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MXC_CCM_CGR1_FEC_MASK |
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MXC_CCM_CGR1_GPIO1_MASK |
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MXC_CCM_CGR1_GPIO2_MASK |
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MXC_CCM_CGR1_GPIO3_MASK |
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MXC_CCM_CGR1_I2C1_MASK |
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MXC_CCM_CGR1_I2C2_MASK |
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MXC_CCM_CGR1_I2C3_MASK,
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&ccm->cgr1);
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/* Set-up NAND */
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__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
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/* Set pinmux for the required peripherals */
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setup_iomux_uart3();
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setup_iomux_i2c();
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setup_iomux_fec();
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setup_iomux_spi();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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2016-10-17 13:51:34 +00:00
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/* Enable power for ethernet */
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gpio_direction_output(63, 0);
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udelay(2000);
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2011-10-23 23:58:20 +00:00
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return 0;
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}
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u32 get_board_rev(void)
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{
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int rev = 0;
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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2016-10-17 13:51:32 +00:00
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/*
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* called prior to booting kernel or by 'fdt boardsetup' command
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*
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*/
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int ft_board_setup(void *blob, bd_t *bd)
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{
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2018-07-19 07:28:23 +00:00
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static const struct node_info nodes[] = {
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2016-10-17 13:51:32 +00:00
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{ "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
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{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
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};
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2017-08-03 18:22:12 +00:00
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if (env_get("fdt_noauto")) {
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2016-10-17 13:51:32 +00:00
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puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
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return 0;
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}
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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return 0;
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}
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