2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2013-12-14 03:47:35 +00:00
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/armv8/mmu.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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*************************************************************************/
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.globl _start
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_start:
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2019-06-13 12:46:44 +00:00
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#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
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2018-01-03 21:31:51 +00:00
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#include <asm/boot0-linux-kernel-header.h>
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#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
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2016-05-31 17:45:06 +00:00
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/*
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* Various SoCs need something special and SoC-specific up front in
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* order to boot, allow them to set that in their boot0.h file and then
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* use it here.
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*/
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#include <asm/arch/boot0.h>
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2017-01-02 11:48:33 +00:00
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#else
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b reset
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2016-05-31 17:45:06 +00:00
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#endif
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2013-12-14 03:47:35 +00:00
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.align 3
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.globl _TEXT_BASE
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_TEXT_BASE:
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2022-10-21 00:22:39 +00:00
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.quad CONFIG_TEXT_BASE
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2013-12-14 03:47:35 +00:00
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/*
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* These are defined in the linker script.
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*/
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.globl _end_ofs
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_end_ofs:
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.quad _end - _start
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.globl _bss_start_ofs
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_bss_start_ofs:
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.quad __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.quad __bss_end - _start
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reset:
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2016-07-18 23:01:50 +00:00
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/* Allow the board to save important registers */
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b save_boot_params
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.globl save_boot_params_ret
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save_boot_params_ret:
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2017-11-03 00:11:27 +00:00
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#if CONFIG_POSITION_INDEPENDENT
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2020-09-09 17:07:25 +00:00
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/* Verify that we're 4K aligned. */
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adr x0, _start
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ands x0, x0, #0xfff
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b.eq 1f
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0:
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/*
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* FATAL, can't continue.
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* U-Boot needs to be loaded at a 4K aligned address.
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*
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* We use ADRP and ADD to load some symbol addresses during startup.
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* The ADD uses an absolute (non pc-relative) lo12 relocation
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* thus requiring 4K alignment.
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*/
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wfi
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b 0b
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1:
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2017-11-03 00:11:27 +00:00
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/*
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* Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
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* executed at a different address than it was linked at.
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*/
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pie_fixup:
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adr x0, _start /* x0 <- Runtime value of _start */
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ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
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2020-09-30 16:39:14 +00:00
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subs x9, x0, x1 /* x9 <- Run-vs-link offset */
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beq pie_fixup_done
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2020-09-09 17:07:26 +00:00
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adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
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add x2, x2, #:lo12:__rel_dyn_start
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adrp x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
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add x3, x3, #:lo12:__rel_dyn_end
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2017-11-03 00:11:27 +00:00
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pie_fix_loop:
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ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
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ldr x4, [x2], #8 /* x4 <- addend */
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cmp w1, #1027 /* relative fixup? */
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bne pie_skip_reloc
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/* relative fix: store addend plus offset at dest location */
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add x0, x0, x9
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add x4, x4, x9
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str x4, [x0]
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pie_skip_reloc:
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cmp x2, x3
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b.lo pie_fix_loop
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pie_fixup_done:
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#endif
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2019-02-20 16:14:49 +00:00
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#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
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armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.
On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.
Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-24 23:57:01 +00:00
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.macro set_vbar, regname, reg
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msr \regname, \reg
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.endm
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adr x0, vectors
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#else
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.macro set_vbar, regname, reg
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.endm
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2015-10-14 16:55:45 +00:00
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#endif
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2013-12-14 03:47:35 +00:00
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/*
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* Could be EL3/EL2/EL1, Initial State:
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* Little Endian, MMU Disabled, i/dCache Disabled
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*/
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switch_el x1, 3f, 2f, 1f
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armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.
On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.
Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-24 23:57:01 +00:00
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3: set_vbar vbar_el3, x0
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2014-04-19 01:45:21 +00:00
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mrs x0, scr_el3
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2014-03-14 06:26:27 +00:00
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orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
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msr scr_el3, x0
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2013-12-14 03:47:35 +00:00
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msr cptr_el3, xzr /* Enable FP/SIMD */
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b 0f
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2021-02-10 19:14:55 +00:00
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2: mrs x1, hcr_el2
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armv8: always use current exception level for TCR_ELx access
Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.
For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.
There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-13 23:11:10 +00:00
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tbnz x1, #HCR_EL2_E2H_BIT, 1f /* HCR_EL2.E2H */
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armv8: Always unmask SErrors
The ARMv8 architecture describes the "SError interrupt" as the fourth
kind of exception, next to synchronous exceptions, IRQs, and FIQs.
Those SErrors signal exceptional conditions from which the system might
not easily recover, and are normally generated by the interconnect as a
response to some bus error. A typical situation is access to a
non-existing memory address or device, but it might be deliberately
triggered by a device as well.
The SError interrupt replaces the Armv7 asynchronous abort.
Trusted Firmware enters U-Boot (BL33) typically with SErrors masked,
and we never enable them. However any SError condition still triggers
the SError interrupt, and this condition stays pending, it just won't be
handled. If now later on the Linux kernel unmasks the "A" bit in PState,
it will immediately take the exception, leading to a kernel crash.
This leaves many people scratching their head about the reason for
this, and leads to long debug sessions, possibly looking at the wrong
places (the kernel, but not U-Boot).
To avoid the situation, just unmask SErrors early in the ARMv8 boot
process, so that the U-Boot exception handlers reports them in a timely
manner. As SErrors are typically asynchronous, the register dump does
not need to point at the actual culprit, but it should happen very
shortly after the condition.
For those exceptions to be taken, we also need to route them to EL2,
if U-Boot is running in this exception level.
This removes the respective code snippet from the Freescale lowlevel
routine, as this is now handled in generic ARMv8 code.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:35 +00:00
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orr x1, x1, #HCR_EL2_AMO_EL2 /* Route SErrors to EL2 */
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msr hcr_el2, x1
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2021-02-10 19:14:55 +00:00
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set_vbar vbar_el2, x0
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2013-12-14 03:47:35 +00:00
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Enable FP/SIMD */
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b 0f
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2021-02-10 19:14:55 +00:00
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1: set_vbar vbar_el1, x0
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2013-12-14 03:47:35 +00:00
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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armv8: Always unmask SErrors
The ARMv8 architecture describes the "SError interrupt" as the fourth
kind of exception, next to synchronous exceptions, IRQs, and FIQs.
Those SErrors signal exceptional conditions from which the system might
not easily recover, and are normally generated by the interconnect as a
response to some bus error. A typical situation is access to a
non-existing memory address or device, but it might be deliberately
triggered by a device as well.
The SError interrupt replaces the Armv7 asynchronous abort.
Trusted Firmware enters U-Boot (BL33) typically with SErrors masked,
and we never enable them. However any SError condition still triggers
the SError interrupt, and this condition stays pending, it just won't be
handled. If now later on the Linux kernel unmasks the "A" bit in PState,
it will immediately take the exception, leading to a kernel crash.
This leaves many people scratching their head about the reason for
this, and leads to long debug sessions, possibly looking at the wrong
places (the kernel, but not U-Boot).
To avoid the situation, just unmask SErrors early in the ARMv8 boot
process, so that the U-Boot exception handlers reports them in a timely
manner. As SErrors are typically asynchronous, the register dump does
not need to point at the actual culprit, but it should happen very
shortly after the condition.
For those exceptions to be taken, we also need to route them to EL2,
if U-Boot is running in this exception level.
This removes the respective code snippet from the Freescale lowlevel
routine, as this is now handled in generic ARMv8 code.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:35 +00:00
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msr daifclr, #0x4 /* Unmask SError interrupts */
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2021-07-12 14:04:21 +00:00
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2022-04-13 09:47:22 +00:00
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#if CONFIG_COUNTER_FREQUENCY
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2021-07-12 14:04:21 +00:00
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branch_if_not_highest_el x0, 4f
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2022-04-13 09:47:22 +00:00
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ldr x0, =CONFIG_COUNTER_FREQUENCY
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2021-07-12 14:04:21 +00:00
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msr cntfrq_el0, x0 /* Initialize CNTFRQ */
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#endif
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4: isb
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2013-12-14 03:47:35 +00:00
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2017-01-06 09:41:10 +00:00
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/*
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2017-04-27 04:36:03 +00:00
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* Enable SMPEN bit for coherency.
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2017-01-06 09:41:10 +00:00
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* This register is not architectural but at the moment
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* this bit should be set for A53/A57/A72.
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*/
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#ifdef CONFIG_ARMV8_SET_SMPEN
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2017-05-15 15:51:59 +00:00
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switch_el x1, 3f, 1f, 1f
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3:
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2017-04-27 04:36:03 +00:00
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mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
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2017-01-06 09:41:10 +00:00
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orr x0, x0, #0x40
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msr S3_1_c15_c2_1, x0
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2020-06-24 01:05:19 +00:00
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isb
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2017-05-15 15:51:59 +00:00
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1:
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2017-01-06 09:41:10 +00:00
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#endif
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2015-01-23 10:20:04 +00:00
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/* Apply ARM core specific erratas */
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bl apply_core_errata
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2014-02-26 21:26:04 +00:00
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/*
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* Cache/BPB/TLB Invalidate
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* i-cache is invalidated before enabled in icache_enable()
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* tlb is invalidated before mmu is enabled in dcache_enable()
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* d-cache is invalidated before enabled in dcache_enable()
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*/
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2013-12-14 03:47:35 +00:00
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/* Processor specific initialization */
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bl lowlevel_init
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2016-12-27 09:19:43 +00:00
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#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
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armv8: Fix and simplify branch_if_master/branch_if_slave
The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.
The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.
Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.
Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:39 +00:00
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branch_if_master x0, master_cpu
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2016-06-27 10:31:05 +00:00
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b spin_table_secondary_jump
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/* never return */
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#elif defined(CONFIG_ARMV8_MULTIENTRY)
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armv8: Fix and simplify branch_if_master/branch_if_slave
The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.
The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.
Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.
Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:39 +00:00
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branch_if_master x0, master_cpu
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2013-12-14 03:47:35 +00:00
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/*
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* Slave CPUs
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*/
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slave_cpu:
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wfe
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ldr x1, =CPU_RELEASE_ADDR
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ldr x0, [x1]
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cbz x0, slave_cpu
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br x0 /* branch to the given address */
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2015-03-09 09:53:21 +00:00
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2016-06-27 10:31:05 +00:00
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master_cpu:
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armv8: Force SP_ELx stack pointer usage
In ARMv8 we have the choice between two stack pointers to use: SP_EL0 or
SP_ELx, which is banked per exception level. This choice is stored in
the SP field of PState, and can be read and set via the SPSel special
register. When the CPU takes an exception, it automatically switches to
the SP_ELx stack pointer.
Trusted Firmware enters U-Boot typically with SPSel set to 1, so we use
SP_ELx all along as our sole stack pointer, both for normal operation and
for exceptions.
But if we now for some reason enter U-Boot with SPSel cleared, we will
setup and use SP_EL0, which is fine, but leaves SP_ELx uninitialised.
When we now take an exception, we try to save the GPRs to some undefined
location, which will usually end badly.
To make sure we always have SP_ELx pointing to some memory, set SPSel
to 1 in the early boot code, to ensure safe operation at all times.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:36 +00:00
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msr SPSel, #1 /* make sure we use SP_ELx */
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2013-12-14 03:47:35 +00:00
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bl _main
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/*-----------------------------------------------------------------------*/
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2015-01-23 10:20:04 +00:00
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WEAK(apply_core_errata)
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mov x29, lr /* Save LR */
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2017-12-28 05:00:55 +00:00
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/* For now, we support Cortex-A53, Cortex-A57 specific errata */
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/* Check if we are running on a Cortex-A53 core */
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branch_if_a53_core x0, apply_a53_core_errata
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2015-01-23 10:20:04 +00:00
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/* Check if we are running on a Cortex-A57 core */
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branch_if_a57_core x0, apply_a57_core_errata
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0:
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mov lr, x29 /* Restore LR */
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ret
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2017-12-28 05:00:55 +00:00
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apply_a53_core_errata:
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#ifdef CONFIG_ARM_ERRATA_855873
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mrs x0, midr_el1
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tst x0, #(0xf << 20)
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b.ne 0b
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mrs x0, midr_el1
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and x0, x0, #0xf
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cmp x0, #3
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b.lt 0b
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Enable data cache clean as data cache clean/invalidate */
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orr x0, x0, #1 << 44
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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2020-06-24 01:05:19 +00:00
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isb
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2017-12-28 05:00:55 +00:00
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#endif
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b 0b
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2015-01-23 10:20:04 +00:00
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apply_a57_core_errata:
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#ifdef CONFIG_ARM_ERRATA_828024
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable non-allocate hint of w-b-n-a memory type */
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2015-05-28 09:24:13 +00:00
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orr x0, x0, #1 << 49
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2015-01-23 10:20:04 +00:00
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/* Disable write streaming no L1-allocate threshold */
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2015-05-28 09:24:13 +00:00
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orr x0, x0, #3 << 25
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2015-01-23 10:20:04 +00:00
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/* Disable write streaming no-allocate threshold */
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2015-05-28 09:24:13 +00:00
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orr x0, x0, #3 << 27
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2015-01-23 10:20:04 +00:00
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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2020-06-24 01:05:19 +00:00
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isb
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2015-01-23 10:20:04 +00:00
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#endif
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#ifdef CONFIG_ARM_ERRATA_826974
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable speculative load execution ahead of a DMB */
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2015-05-28 09:24:13 +00:00
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orr x0, x0, #1 << 59
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2015-01-23 10:20:04 +00:00
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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2020-06-24 01:05:19 +00:00
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isb
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2015-01-23 10:20:04 +00:00
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#endif
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2016-01-27 12:39:32 +00:00
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#ifdef CONFIG_ARM_ERRATA_833471
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* FPSCR write flush.
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* Note that in some cases where a flush is unnecessary this
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could impact performance. */
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orr x0, x0, #1 << 38
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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2020-06-24 01:05:19 +00:00
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isb
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2016-01-27 12:39:32 +00:00
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#endif
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#ifdef CONFIG_ARM_ERRATA_829520
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable Indirect Predictor bit will prevent this erratum
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from occurring
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* Note that in some cases where a flush is unnecessary this
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could impact performance. */
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orr x0, x0, #1 << 4
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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2020-06-24 01:05:19 +00:00
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isb
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2016-01-27 12:39:32 +00:00
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#endif
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2015-01-23 10:20:04 +00:00
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#ifdef CONFIG_ARM_ERRATA_833069
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable Enable Invalidates of BTB bit */
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and x0, x0, #0xE
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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2020-06-24 01:05:19 +00:00
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isb
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2015-01-23 10:20:04 +00:00
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#endif
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b 0b
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ENDPROC(apply_core_errata)
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/*-----------------------------------------------------------------------*/
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2013-12-14 03:47:35 +00:00
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WEAK(lowlevel_init)
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mov x29, lr /* Save LR */
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2014-03-14 06:26:27 +00:00
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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2016-04-28 18:45:44 +00:00
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#endif
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2014-03-14 06:26:27 +00:00
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2016-05-20 03:13:10 +00:00
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#ifdef CONFIG_ARMV8_MULTIENTRY
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armv8: Fix and simplify branch_if_master/branch_if_slave
The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.
The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.
Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.
Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:39 +00:00
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branch_if_master x0, 2f
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2013-12-14 03:47:35 +00:00
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent salves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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2014-03-14 06:26:27 +00:00
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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2013-12-14 03:47:35 +00:00
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/*
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2014-03-14 06:26:27 +00:00
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* All slaves will enter EL2 and optionally EL1.
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2013-12-14 03:47:35 +00:00
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*/
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2017-01-17 01:39:17 +00:00
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adr x4, lowlevel_in_el2
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ldr x5, =ES_TO_AARCH64
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2013-12-14 03:47:35 +00:00
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bl armv8_switch_to_el2
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2016-11-10 02:49:03 +00:00
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lowlevel_in_el2:
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2013-12-14 03:47:35 +00:00
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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2017-01-17 01:39:17 +00:00
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adr x4, lowlevel_in_el1
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ldr x5, =ES_TO_AARCH64
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2013-12-14 03:47:35 +00:00
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bl armv8_switch_to_el1
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2016-11-10 02:49:03 +00:00
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lowlevel_in_el1:
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2013-12-14 03:47:35 +00:00
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#endif
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2015-03-09 09:53:21 +00:00
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2014-03-14 06:26:27 +00:00
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2:
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2013-12-14 03:47:35 +00:00
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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2014-03-14 06:26:27 +00:00
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WEAK(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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ldr x0, =GICD_BASE
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2016-06-17 09:32:47 +00:00
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b gic_kick_secondary_cpus
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2014-03-14 06:26:27 +00:00
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#endif
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ret
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ENDPROC(smp_kick_all_cpus)
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2013-12-14 03:47:35 +00:00
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/*-----------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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2019-02-20 16:14:49 +00:00
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#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
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2013-12-14 03:47:35 +00:00
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/* Relocate vBAR */
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adr x0, vectors
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switch_el x1, 3f, 2f, 1f
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3: msr vbar_el3, x0
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b 0f
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2: msr vbar_el2, x0
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b 0f
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1: msr vbar_el1, x0
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0:
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armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.
On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.
Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-24 23:57:01 +00:00
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#endif
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2013-12-14 03:47:35 +00:00
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ret
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ENDPROC(c_runtime_cpu_setup)
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2016-07-18 23:01:50 +00:00
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WEAK(save_boot_params)
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b save_boot_params_ret /* back to my caller */
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ENDPROC(save_boot_params)
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