2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2013-12-26 04:14:17 +00:00
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/*
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* (C) Copyright 2013 SAMSUNG Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*/
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#include <common.h>
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#include <cros_ec.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <spi.h>
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#include <tmu.h>
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#include <netdev.h>
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#include <asm/io.h>
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2014-10-21 01:48:37 +00:00
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#include <asm/gpio.h>
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2013-12-26 04:14:17 +00:00
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#include <asm/arch/board.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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2014-09-05 11:23:30 +00:00
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#include <asm/arch/system.h>
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2013-12-26 04:14:17 +00:00
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#include <asm/arch/sromc.h>
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2014-03-07 13:59:45 +00:00
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#include <lcd.h>
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2015-04-20 18:07:50 +00:00
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#include <i2c.h>
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2015-03-03 16:32:03 +00:00
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#include <usb.h>
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2015-05-22 16:14:24 +00:00
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#include <dwc3-uboot.h>
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#include <samsung/misc.h>
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2016-04-23 16:48:14 +00:00
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#include <dm/pinctrl.h>
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#include <dm.h>
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2013-12-26 04:14:17 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2014-10-08 20:57:28 +00:00
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__weak int exynos_early_init_f(void)
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2014-03-07 13:59:43 +00:00
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{
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return 0;
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}
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2014-10-08 20:57:28 +00:00
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__weak int exynos_power_init(void)
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2014-03-07 13:59:43 +00:00
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{
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return 0;
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}
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2013-12-26 04:14:17 +00:00
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#if defined CONFIG_EXYNOS_TMU
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/* Boot Time Thermal Analysis for SoC temperature threshold breach */
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static void boot_temp_check(void)
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{
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int temp;
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switch (tmu_monitor(&temp)) {
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case TMU_STATUS_NORMAL:
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break;
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case TMU_STATUS_TRIPPED:
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/*
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* Status TRIPPED ans WARNING means corresponding threshold
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* breach
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*/
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puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
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set_ps_hold_ctrl();
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hang();
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break;
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case TMU_STATUS_WARNING:
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puts("EXYNOS_TMU: WARNING! Temperature very high\n");
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break;
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case TMU_STATUS_INIT:
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/*
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* TMU_STATUS_INIT means something is wrong with temperature
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* sensing and TMU status was changed back from NORMAL to INIT.
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*/
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puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
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break;
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default:
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debug("EXYNOS_TMU: Unknown TMU state\n");
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}
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
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#if defined CONFIG_EXYNOS_TMU
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if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
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debug("%s: Failed to init TMU\n", __func__);
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return -1;
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}
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boot_temp_check();
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#endif
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2015-02-17 13:50:25 +00:00
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#ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE
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/* The last few MB of memory can be reserved for secure firmware */
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ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE;
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2013-12-26 04:14:17 +00:00
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2015-02-17 13:50:25 +00:00
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gd->ram_size -= size;
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gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
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#endif
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2013-12-26 04:14:17 +00:00
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return exynos_init();
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}
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int dram_init(void)
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{
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2015-03-04 09:54:48 +00:00
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unsigned int i;
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2016-04-23 16:48:14 +00:00
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unsigned long addr;
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2013-12-26 04:14:17 +00:00
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
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gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
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}
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return 0;
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}
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2017-03-31 14:40:32 +00:00
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int dram_init_banksize(void)
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2013-12-26 04:14:17 +00:00
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{
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2015-03-04 09:54:48 +00:00
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unsigned int i;
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2016-04-23 16:48:14 +00:00
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unsigned long addr, size;
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2013-12-26 04:14:17 +00:00
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
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size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
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gd->bd->bi_dram[i].start = addr;
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gd->bd->bi_dram[i].size = size;
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}
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2017-03-31 14:40:32 +00:00
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return 0;
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2013-12-26 04:14:17 +00:00
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}
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static int board_uart_init(void)
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{
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2016-04-23 16:48:14 +00:00
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#ifndef CONFIG_PINCTRL_EXYNOS
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2013-12-26 04:14:17 +00:00
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int err, uart_id, ret = 0;
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for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
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err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART%d not configured\n",
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(uart_id - PERIPH_ID_UART0));
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ret |= err;
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}
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}
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return ret;
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2016-04-23 16:48:14 +00:00
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#else
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return 0;
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#endif
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2013-12-26 04:14:17 +00:00
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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int err;
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2014-09-01 11:50:49 +00:00
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#ifdef CONFIG_BOARD_TYPES
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set_board_type();
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#endif
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2013-12-26 04:14:17 +00:00
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err = board_uart_init();
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if (err) {
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debug("UART init failed\n");
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return err;
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}
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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board_i2c_init(gd->fdt_blob);
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#endif
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2014-09-05 11:23:30 +00:00
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2014-03-07 13:59:43 +00:00
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return exynos_early_init_f();
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2013-12-26 04:14:17 +00:00
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}
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#endif
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2015-04-20 18:07:50 +00:00
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#if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC)
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2013-12-26 04:14:17 +00:00
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int power_init_board(void)
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{
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set_ps_hold_ctrl();
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2014-03-07 13:59:43 +00:00
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return exynos_power_init();
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2013-12-26 04:14:17 +00:00
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}
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#endif
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2014-03-07 13:59:45 +00:00
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#ifdef CONFIG_SMC911X
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2013-12-26 04:14:17 +00:00
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static int decode_sromc(const void *blob, struct fdt_sromc *config)
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{
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int err;
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int node;
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node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
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if (node < 0) {
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debug("Could not find SROMC node\n");
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return node;
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}
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config->bank = fdtdec_get_int(blob, node, "bank", 0);
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config->width = fdtdec_get_int(blob, node, "width", 2);
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err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
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FDT_SROM_TIMING_COUNT);
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if (err < 0) {
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debug("Could not decode SROMC configuration Error: %s\n",
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fdt_strerror(err));
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return -FDT_ERR_NOTFOUND;
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}
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return 0;
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}
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2014-03-07 13:59:45 +00:00
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#endif
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2013-12-26 04:14:17 +00:00
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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u32 smc_bw_conf, smc_bc_conf;
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struct fdt_sromc config;
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fdt_addr_t base_addr;
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int node;
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node = decode_sromc(gd->fdt_blob, &config);
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if (node < 0) {
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debug("%s: Could not find sromc configuration\n", __func__);
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return 0;
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}
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node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
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if (node < 0) {
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debug("%s: Could not find lan9215 configuration\n", __func__);
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return 0;
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}
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/* We now have a node, so any problems from now on are errors */
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base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
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if (base_addr == FDT_ADDR_T_NONE) {
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debug("%s: Could not find lan9215 address\n", __func__);
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return -1;
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}
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/* Ethernet needs data bus width of 16 bits */
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if (config.width != 2) {
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debug("%s: Unsupported bus width %d\n", __func__,
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config.width);
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return -1;
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}
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smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
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| SROMC_BYTE_ENABLE(config.bank);
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smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
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SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
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SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
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SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
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SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
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SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
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SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
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/* Select and configure the SROMC bank */
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exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
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s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
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return smc911x_initialize(0, base_addr);
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#endif
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return 0;
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}
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2019-03-06 18:37:52 +00:00
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#if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE)
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2014-03-07 13:59:42 +00:00
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int checkboard(void)
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{
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2019-01-12 01:37:07 +00:00
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if (IS_ENABLED(CONFIG_BOARD_TYPES)) {
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2019-03-06 18:37:51 +00:00
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const char *board_info;
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if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
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/*
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* Printing type requires having revision, although
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* this will succeed only if done late.
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* Otherwise revision will be set in misc_init_r().
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*/
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set_board_revision();
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}
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board_info = get_board_type();
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2019-01-12 01:37:07 +00:00
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if (board_info)
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printf("Type: %s\n", board_info);
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}
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2014-03-07 13:59:42 +00:00
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return 0;
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}
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2013-12-26 04:14:17 +00:00
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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2018-11-06 22:21:26 +00:00
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struct udevice *dev;
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int ret;
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2013-12-26 04:14:17 +00:00
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2018-11-06 22:21:26 +00:00
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stdio_print_current_devices();
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ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
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if (ret && ret != -ENODEV) {
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2013-12-26 04:14:17 +00:00
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/* Force console on */
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gd->flags &= ~GD_FLG_SILENT;
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2018-11-06 22:21:26 +00:00
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printf("cros-ec communications failure %d\n", ret);
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2013-12-26 04:14:17 +00:00
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puts("\nPlease reset with Power+Refresh\n\n");
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panic("Cannot init cros-ec device");
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return -1;
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}
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return 0;
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}
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#endif
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2014-03-07 13:59:45 +00:00
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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2019-03-06 18:37:51 +00:00
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if (IS_ENABLED(CONFIG_BOARD_TYPES) &&
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!IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
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/*
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* If revision was not set by late display boardinfo,
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* set it here. At this point regulators should be already
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* available.
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*/
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set_board_revision();
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}
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2014-03-07 13:59:45 +00:00
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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set_board_info();
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#endif
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#ifdef CONFIG_LCD_MENU
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keys_init();
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check_boot_mode();
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#endif
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#ifdef CONFIG_CMD_BMP
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if (panel_info.logo_on)
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draw_logo();
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#endif
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return 0;
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}
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#endif
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2015-01-15 02:45:56 +00:00
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void reset_misc(void)
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{
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struct gpio_desc gpio = {};
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int node;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
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"samsung,emmc-reset");
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|
|
if (node < 0)
|
|
|
|
return;
|
|
|
|
|
2017-05-31 03:47:09 +00:00
|
|
|
gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0,
|
|
|
|
&gpio, GPIOD_IS_OUT);
|
2015-01-15 02:45:56 +00:00
|
|
|
|
|
|
|
if (dm_gpio_is_valid(&gpio)) {
|
|
|
|
/*
|
|
|
|
* Reset eMMC
|
|
|
|
*
|
|
|
|
* FIXME: Need to optimize delay time. Minimum 1usec pulse is
|
|
|
|
* required by 'JEDEC Standard No.84-A441' (eMMC)
|
|
|
|
* document but real delay time is expected to greater
|
|
|
|
* than 1usec.
|
|
|
|
*/
|
|
|
|
dm_gpio_set_value(&gpio, 0);
|
|
|
|
mdelay(10);
|
|
|
|
dm_gpio_set_value(&gpio, 1);
|
|
|
|
}
|
|
|
|
}
|
2015-03-03 16:32:03 +00:00
|
|
|
|
|
|
|
int board_usb_cleanup(int index, enum usb_init_type init)
|
|
|
|
{
|
2015-05-22 16:14:24 +00:00
|
|
|
#ifdef CONFIG_USB_DWC3
|
|
|
|
dwc3_uboot_exit(index);
|
|
|
|
#endif
|
2015-03-03 16:32:03 +00:00
|
|
|
return 0;
|
|
|
|
}
|