mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 01:19:49 +00:00
23 lines
515 B
Text
23 lines
515 B
Text
|
gdsys AXI busses of IHS FPGA devices
|
||
|
|
|
||
|
|
Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which
|
||
|
|
the connected devices (usually IP cores) can be controlled via software.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible: must be "gdsys,ihs_axi"
|
||
|
|
- reg: describes the address and length of the AXI bus's register map (within
|
||
|
|
the FPGA's register space)
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
fpga0_axi_video0 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "gdsys,ihs_axi";
|
||
|
|
reg = <0x170 0x10>;
|
||
|
|
|
||
|
|
axi_dev_1 {
|
||
|
|
...
|
||
|
|
};
|
||
|
|
};
|