2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2011-12-23 05:51:29 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2011
|
|
|
|
* Graeme Russ, <graeme.russ@gmail.com>
|
|
|
|
*/
|
2015-08-13 07:29:10 +00:00
|
|
|
|
2011-12-23 05:51:29 +00:00
|
|
|
#include <common.h>
|
2016-09-21 02:28:55 +00:00
|
|
|
#include <linux/errno.h>
|
2015-01-01 23:18:11 +00:00
|
|
|
#include <asm/mtrr.h>
|
2011-12-23 05:51:29 +00:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2013-02-28 19:26:10 +00:00
|
|
|
/* Get the top of usable RAM */
|
|
|
|
__weak ulong board_get_usable_ram_top(ulong total_size)
|
2011-12-23 10:14:22 +00:00
|
|
|
{
|
2013-02-28 19:26:10 +00:00
|
|
|
return gd->ram_size;
|
|
|
|
}
|
|
|
|
|
2011-12-23 10:14:22 +00:00
|
|
|
int init_cache_f_r(void)
|
|
|
|
{
|
2019-04-26 03:59:06 +00:00
|
|
|
#if (CONFIG_IS_ENABLED(X86_32BIT_INIT) || \
|
|
|
|
(!defined(CONFIG_SPL_BUILD) && \
|
|
|
|
!CONFIG_IS_ENABLED(CONFIG_X86_RUN_64BIT))) && \
|
|
|
|
!defined(CONFIG_HAVE_FSP)
|
2015-01-01 23:18:11 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mtrr_commit(false);
|
2015-01-22 03:29:41 +00:00
|
|
|
/* If MTRR MSR is not implemented by the processor, just ignore it */
|
|
|
|
if (ret && ret != -ENOSYS)
|
2015-01-01 23:18:11 +00:00
|
|
|
return ret;
|
|
|
|
#endif
|
2011-12-23 10:14:22 +00:00
|
|
|
/* Initialise the CPU cache(s) */
|
|
|
|
return init_cache();
|
|
|
|
}
|