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u-boot/drivers/clk/at91/clk-utmi.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
/*
* Copyright (C) 2016 Atmel Corporation
* Wenyou.Yang <wenyou.yang@atmel.com>
*/
#include <common.h>
#include <clk-uclass.h>
dm: Use dm.h header when driver mode is used This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-17 23:18:03 +00:00
#include <dm.h>
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
#include <syscon.h>
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
#include <linux/io.h>
#include <mach/at91_pmc.h>
ARM: at91: Rename sama5_sfr.h to at91_sfr.h The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-09-27 13:09:00 +00:00
#include <mach/at91_sfr.h>
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
#include "pmc.h"
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
/*
* The purpose of this clock is to generate a 480 MHz signal. A different
* rate can't be configured.
*/
#define UTMI_RATE 480000000
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
static int utmi_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
struct clk clk_dev;
ulong clk_rate;
u32 utmi_ref_clk_freq;
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
u32 tmp;
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
int err;
clk: at91: utmi: add timeout for utmi lock In case the slow clock is not properly configured, the UTMI clock cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles". In this case U-boot will loop indefinitely. Added a timeout in this case, to start U-boot even if UTMI clock is not enabled, so the user can use different media if needed, or investigate. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-08-03 09:10:49 +00:00
int timeout = 2000000;
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
if (readl(&pmc->sr) & AT91_PMC_LOCKU)
return 0;
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
/*
* If mainck rate is different from 12 MHz, we have to configure the
* FREQ field of the SFR_UTMICKTRIM register to generate properly
* the utmi clock.
*/
err = clk_get_by_index(clk->dev, 0, &clk_dev);
if (err)
return -EINVAL;
clk_rate = clk_get_rate(&clk_dev);
switch (clk_rate) {
case 12000000:
utmi_ref_clk_freq = 0;
break;
case 16000000:
utmi_ref_clk_freq = 1;
break;
case 24000000:
utmi_ref_clk_freq = 2;
break;
/*
* Not supported on SAMA5D2 but it's not an issue since MAINCK
* maximum value is 24 MHz.
*/
case 48000000:
utmi_ref_clk_freq = 3;
break;
default:
printf("UTMICK: unsupported mainck rate\n");
return -EINVAL;
}
if (plat->regmap_sfr) {
err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
if (err)
return -EINVAL;
tmp &= ~AT91_UTMICKTRIM_FREQ;
tmp |= utmi_ref_clk_freq;
err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
if (err)
return -EINVAL;
} else if (utmi_ref_clk_freq) {
printf("UTMICK: sfr node required\n");
return -EINVAL;
}
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
tmp = readl(&pmc->uckr);
tmp |= AT91_PMC_UPLLEN |
AT91_PMC_UPLLCOUNT |
AT91_PMC_BIASEN;
writel(tmp, &pmc->uckr);
clk: at91: utmi: add timeout for utmi lock In case the slow clock is not properly configured, the UTMI clock cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles". In this case U-boot will loop indefinitely. Added a timeout in this case, to start U-boot even if UTMI clock is not enabled, so the user can use different media if needed, or investigate. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-08-03 09:10:49 +00:00
while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
;
clk: at91: utmi: add timeout for utmi lock In case the slow clock is not properly configured, the UTMI clock cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles". In this case U-boot will loop indefinitely. Added a timeout in this case, to start U-boot even if UTMI clock is not enabled, so the user can use different media if needed, or investigate. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-08-03 09:10:49 +00:00
if (!timeout) {
printf("UTMICK: timeout waiting for UPLL lock\n");
return -ETIMEDOUT;
}
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
return 0;
}
static ulong utmi_clk_get_rate(struct clk *clk)
{
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
/* UTMI clk rate is fixed. */
return UTMI_RATE;
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
}
static struct clk_ops utmi_clk_ops = {
.enable = utmi_clk_enable,
.get_rate = utmi_clk_get_rate,
};
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
{
struct pmc_platdata *plat = dev_get_platdata(dev);
struct udevice *syscon;
uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
"regmap-sfr", &syscon);
if (syscon)
plat->regmap_sfr = syscon_get_regmap(syscon);
return 0;
}
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
static int utmi_clk_probe(struct udevice *dev)
{
return at91_pmc_core_probe(dev);
}
static const struct udevice_id utmi_clk_match[] = {
{ .compatible = "atmel,at91sam9x5-clk-utmi" },
{}
};
U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
.name = "at91sam9x5-utmi-clk",
.id = UCLASS_CLK,
.of_match = utmi_clk_match,
.probe = utmi_clk_probe,
clk: at91: utmi: Set the reference clock frequency By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-05 10:30:07 +00:00
.ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
.ops = &utmi_clk_ops,
};
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