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u-boot/drivers/mtd/spi/spi-nor-ids.c

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mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
*
* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
* Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <common.h>
#include <spi.h>
#include <spi_flash.h>
#include "sf_internal.h"
/* Exclude chip names for SPL to save space */
#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
#define INFO_NAME(_name) .name = _name,
#else
#define INFO_NAME(_name)
#endif
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
INFO_NAME(_name) \
.id = { \
((_jedec_id) >> 16) & 0xff, \
((_jedec_id) >> 8) & 0xff, \
(_jedec_id) & 0xff, \
((_ext_id) >> 8) & 0xff, \
(_ext_id) & 0xff, \
}, \
.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
.sector_size = (_sector_size), \
.n_sectors = (_n_sectors), \
.page_size = 256, \
.flags = (_flags),
#define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
INFO_NAME(_name) \
.id = { \
((_jedec_id) >> 16) & 0xff, \
((_jedec_id) >> 8) & 0xff, \
(_jedec_id) & 0xff, \
((_ext_id) >> 16) & 0xff, \
((_ext_id) >> 8) & 0xff, \
(_ext_id) & 0xff, \
}, \
.id_len = 6, \
.sector_size = (_sector_size), \
.n_sectors = (_n_sectors), \
.page_size = 256, \
.flags = (_flags),
/* NOTE: double check command sets and memory organization when you add
* more nor chips. This current list focusses on newer chips, which
* have been converging on command sets which including JEDEC ID.
*
* All newly added entries should describe *hardware* and should use SECT_4K
* (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
* scenarios excluding small sectors there is config option that can be
mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-26 13:34:27 +00:00
* disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS.
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
* For historical (and compatibility) reasons (before we got above config) some
* old entries may be missing 4K flag.
*/
const struct flash_info spi_nor_ids[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
/* Atmel -- some are (confusingly) marketed as "DataFlash" */
{ INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
{ INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
spi-nor-ids: Add support for Adesto AT25SL321 Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-21 13:51:16 +00:00
{ INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-27 15:42:39 +00:00
{ INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
/* EON -- en25xxx */
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
/* GigaDevice */
{
INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add Gigadevice GD25LQ64C Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on rk3399-gru-kevin: => sf probe SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB => sf erase 0x600000 0x200000 SF: 2097152 bytes @ 0x600000 Erased: OK => sf test 0x700000 0x1000 SPI flash test: 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps Test passed 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps The values are the same as in Linux, except adjusted for the U-Boot definition of INFO(). Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-31 16:20:12 +00:00
{
INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor: ids: Add GigaDevice gd25q128 Add gd25q128 128Mbit chip to spi-nor id table. Tested on Pinebook Pro Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-11-14 00:01:22 +00:00
{
INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add Gigadevice gd25lq128 ID This adds support for the Gigadevice gd25lq128 ID needed on the upcoming libretech-ac board. SPI_NOR_QUAD_READ is not set since it has not been tested in Quad mode. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12 09:50:10 +00:00
{
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
mtd: spi-nor-ids: Enable quad read for Gigadevice gd25lq128 The Gigadevice gd25lq128 serial flash exists in different versions, all which identify themselves using the same JEDEC id. gd25lq128c: https://www.gigadevice.com/datasheet/gd25lq128 gd25lq128d: https://www.gigadevice.com/datasheet/gd25lq128d However, all versions support quad read, so enable it. Tested and verified on the Sipeed MAix BiT board. Fixes: 30b9a28a3f2d ("mtd: spi-nor-ids: Add Gigadevice gd25lq128 ID") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-03-03 18:26:39 +00:00
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
mtd: spi-nor-ids: Add Gigadevice gd25lq128 ID This adds support for the Gigadevice gd25lq128 ID needed on the upcoming libretech-ac board. SPI_NOR_QUAD_READ is not set since it has not been tested in Quad mode. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12 09:50:10 +00:00
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add GD25LQ256D Chip Add Gigadevice GD25LQ256D SPI NOR chip. https://www.gigadevice.com/datasheet/gd25lq256d/ Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [jagan: updated commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-09-30 11:53:01 +00:00
{
INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
{ INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
{ INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
{ INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
{ INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ) },
mtd: spi-nor-ids: Add is25lp512 and is25wp512 devices Add is25lp512 and is25wp512 devices to spi-nor id table Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> [jagan: droped Tested-by of patch author] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-18 10:26:50 +00:00
{ INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
{ INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor: ids: Add is25wp256 chip Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-29 07:42:37 +00:00
{ INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256 IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-20 10:06:07 +00:00
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES) },
mtd: spi-nor-ids: Add is25lp512 and is25wp512 devices Add is25lp512 and is25wp512 devices to spi-nor id table Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> [jagan: droped Tested-by of patch author] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-18 10:26:50 +00:00
{ INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
{ INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) },
{ INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) },
{ INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
mtd: spi: Add Macronix MX25U3235F device Add Macronix MX25U3235F flash device description. This is a 4MiB part. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-03-20 21:20:09 +00:00
{ INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
mtd: spi-nor-ids: Add SECT_4K to mx25l12805d According to the mx25l12805d datasheet it supports using 4K or 64K sectors. So lets add the SECT_4K to enable 4K sector usage. Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-23 08:52:38 +00:00
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
mtd: spi-nor-ids: add support for Macronix mx25u12835f flash Some of Marvell A3700 boards use mx25u12835f, specifically uDPU and ESPRESSObin v7. Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> [a.heider: adapt commit message to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-09-07 06:54:58 +00:00
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
mtd: spi-nor-ids: add Macronix mx25u51245g flash entry Add Macronix mx25u51245g flash entry, so this can be used on SoCFPGA devices. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> [Jagan: updated commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-04-27 03:56:28 +00:00
{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
mtd: spi-nor-ids: Add support for Macronix MX25V8035F and MX25R1635F The MX25V8035F is a 8Mb SPI NOR flash and the MX25R1635F is very similar, but has twice the size (16Mb) and supports a wider supply voltage range. They were tested on the Kontron Electronics i.MX6UL and i.MX8MM SoMs. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-06-07 12:36:41 +00:00
{ INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add Macronix MX66U2G45F device Add Macronix MX66U2G45F flash device description. This is a 256 MiB part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Vignesh R <vigneshr@ti.com> [jagan: use 'g' instead of 'f' in flash name] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-07 22:27:46 +00:00
{ INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters array On i.mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03 13:02:56 +00:00
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
mtd: spi-nor-core: Add support for Macronix Octal flash Adding Macronix Octal flash for Octal DTR support. The octaflash series can be divided into the following types: MX25 series : Serial NOR Flash. MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb) LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation. LW/UW series : Support simultaneous Read-while-Write operation in multiple bank architecture. Read-while-write feature which means read data one bank while another bank is programing or erasing. MX25LM : 3.0V Octal I/O -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf MX25UM : 1.8V Octal I/O -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf MX66LM : 3.0V Octal I/O with stacked die -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf MX66UM : 1.8V Octal I/O with stacked die -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf MX25LW : 3.0V Octal I/O with Read-while-Write MX25UW : 1.8V Octal I/O with Read-while-Write MX66LW : 3.0V Octal I/O with Read-while-Write and stack die MX66UW : 1.8V Octal I/O with Read-while-Write and stack die About LW/UW series, please contact us freely if you have any questions. For adding Octal NOR Flash IDs, we have validated each Flash on plateform zynq-picozed. As below are the SFDP table dump. zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2943c zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx66uw2g345gx0 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw2g345gx0 zynq> hexdump mx66uw2g345gx0 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 7fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7987 0001 1284 e200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 001f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2853b zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx66lm1g45g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66lm1g45g zynq> hexdump mx66lm1g45g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 6987 0001 1282 e200 02cc 3867 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 6666 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000 0000130 3514 001c 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2853a zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25lm51245g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lm51245g zynq> hexdump mx25lm51245g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7989 0001 128d e200 02cc 4467 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 6666 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000 0000130 3514 001c 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2863a zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25lw51245g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lw51245g zynq> hexdump mx25lw51245g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 0000 0000 0000 0000 0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f e200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 6666 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000 0000130 3514 001c 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28539 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25lm25645g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lm25645g zynq> hexdump mx25lm25645g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 6987 0001 1282 d200 02cc 3867 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 6666 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000 0000130 3514 001c 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2843c zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx66uw2g345g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw2g345g zynq> hexdump mx66uw2g345g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 7fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7987 0001 1284 e200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 001f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2803b zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx66um1g45g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66um1g45g zynq> hexdump mx66um1g45g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7989 0001 128d e200 02cc 4467 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 3514 809c 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2813b zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx66uw1g45g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw1g45g zynq> hexdump mx66uw1g45g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f e200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2813a zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw51245g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw51245g zynq> hexdump mx25uw51245g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f e200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 7777 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2843a zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw51345g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw51345g zynq> hexdump mx25uw51345g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f e200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28039 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25um25645g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25um25645g zynq> random: fast init done zynq> hexdump mx25um25645g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7987 0001 1284 d200 02cc 3867 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 3514 809c 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28139 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw25645g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw25645g zynq> hexdump mx25uw25645g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7989 0001 128d d200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28339 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25um25345g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25um25345g zynq> hexdump mx25um25345g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 6987 0001 1282 d200 02cc 3867 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0904 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28439 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw25345g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw25345g zynq> hexdump mx25uw25345g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7987 0001 1284 d200 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28138 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw12845g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw12845g zynq> hexdump mx25uw12845g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 0000 0000 0000 0000 0000040 20e5 ff8a ffff 07ff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f c900 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28438 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw12345g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw12345g zynq> hexdump mx25uw12345g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 07ff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f c900 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28137 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw6445g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw6445g zynq> hexdump mx25uw6445g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 03ff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 7989 0001 128d c400 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 a37c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c28437 zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw6345g zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw6345g zynq> hexdump mx25uw6345g 0000000 4653 5044 0108 fd04 0700 1401 0040 ff00 0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00 0000020 0005 0501 0120 ff00 0084 0201 0134 ff00 0000030 0000 0000 0000 0000 ffff ffff ffff ffff 0000040 20e5 ff8a ffff 03ff ff00 ff00 ff00 ff00 0000050 ffee ffff ffff ff00 ffff ff00 200c d810 0000060 ff00 ff00 798b 0001 128f c400 04cc 4667 0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000 0000080 0000 0000 0000 237c 0048 0000 0000 8888 0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff 00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600 00000b0 7172 b803 7172 b803 0000 0000 a390 8218 00000c0 c000 9669 0000 0000 0000 0000 7172 9800 00000d0 7172 b800 7172 9900 0000 0000 7172 9800 00000e0 7172 f800 7172 9900 7172 f900 0000 0000 00000f0 0000 0000 1501 d001 7172 d806 0000 5086 0000100 0000 0106 0000 0000 0002 0301 0200 0000 0000110 0000 0106 0000 0000 0000 0672 0200 0000 0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000 0000130 4514 8098 0643 000f dc21 ffff ffff ffff 0000140 ffff ffff ffff ffff ffff ffff ffff ffff Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-07-18 06:49:22 +00:00
{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* Micron */
{ INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-11 07:58:20 +00:00
{ INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
mtd: spi: Add flash property for Micron mt25qu512a mt25qu512a is rebranded after its spinoff from STM, so it is different only in term of extended jedec ID, initial JEDEC id is same as that of n25q512a.In order to avoid any confussion with respect to name new entry is added. This flash is tested for Single I/O mode on LS1046FRWY although it also support QUAD I/O. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-17 06:15:00 +00:00
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
mtd: spi-nor-ids: Add SECT_4K to mt25qu512a The mt25qu512a supports 4K or 64K sectors, so adding SECT_4K to enable 4K sector usage. Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> [jagan: droped Tested-by of patch author and datasheet link] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-18 10:30:18 +00:00
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-11 07:58:20 +00:00
USE_FSR) },
spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-11 07:58:18 +00:00
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
spi-nor: spi-nor-ids: Add entries for mt25q variants mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-11 07:58:19 +00:00
{ INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-11 07:58:18 +00:00
{ INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
mtd: spi-nor-ids: add Micron MT25QL01G flash Add Micron MT25QL01G flash, used on AST2600 board. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-07 22:40:01 +00:00
{ INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
mtd: spi-nor-ids: Reinstate Micron MT25QL02G This ID disappeared in 5b66fdb29dc ("mtd: spi: Remove unused files"), add the ID back, since the chip is used on devices supported by U-Boot. Fixes: 5b66fdb29dc ("mtd: spi: Remove unused files") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-05 08:58:47 +00:00
{ INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode Since this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-25 19:17:29 +00:00
#ifdef CONFIG_SPI_FLASH_MT35XU
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode Since this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-25 19:17:29 +00:00
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
mtd: spi-nor-ids: Enable SPI_NOR_OCTAL_READ flag for mt35xu* Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") enables octal mode(1-1-8) support in spi-nor framework. mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable SPI_NOR_OCTAL_READ flag for these flashes. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-03-14 12:53:54 +00:00
{ INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
* for the chips listed here (without boot sectors).
*/
{ INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor: Enable dual and quad read for s25fl256s0 The s25fl256s0 supports dual and quad read like s25fl256s1. Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags to the flash_info entry. Tested on real silicon and confirmed to be working. Signed-off-by: Bacem Daassi <Bacem.Daassi@cypress.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-03-27 18:58:14 +00:00
{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
mtd: spi-nor-ids: Add Spansion s25fs512s flash entry Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-03 06:57:42 +00:00
{ INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
{ INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
{ INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) },
{ INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) },
{ INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) },
{ INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) },
{ INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
mtd: add spi flash id s25fl064l Add support for SPANSION s25fl064l Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Vignesh R <vigneshr@ti.com>
2019-02-08 10:03:39 +00:00
{ INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi-nor: Add support for Spansion S25FL256L The S25FL256L is a part of the S25FL-L family and has the same feature set as S25FL128L except the density. The datasheet can be found in the following link. https://www.cypress.com/file/316171/download The S25FL256L is 32MB NOR Flash that does not support Bank Address Register. This fixup is activated if CONFIG_SPI_FLASH_BAR is enabled and returns ENOTSUPP in setup() hook to avoid further ops. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
2021-09-30 02:23:37 +00:00
{ INFO("s25fl256l", 0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable sector architecture. By default, the 512Mb and 1Gb, single-die package parts are configured to non-uniform that 4KB sectors overlaid on bottom address. To support this, an erase hook makes overlaid sectors appear as uniform sectors. The 2Gb, dual-die package parts are configured to uniform by default. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29 06:00:57 +00:00
{ INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi-nor: Add support for Infineon s25fs256t Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and differences comparing to other Spansion/Cypress flash familes are: - 4-byte address mode by factory default - Quad mode is enabled by factory default - Supports mixture of 128KB and 64KB sectors by OTP configuration (this patch supports uniform 128KB only) Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-12-19 01:28:21 +00:00
{ INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
mtd: spi-nor-core: Rename configuration macro for S28 support Change configuration macro name to support all other devices in SEMPER S28 family. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-08-25 07:48:47 +00:00
#ifdef CONFIG_SPI_FLASH_S28HX_T
mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt. These devices have the same functionality as s28hs512t. In spi-nor-core, use device ID byte to detect S28 family instead of device name. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-08-25 07:48:48 +00:00
{ INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
mtd: spi-nor-core: Add support for Cypress Semper flash The Cypress Semper flash is an xSPI compliant octal DTR flash. Add support for using it in octal DTR mode. The flash by default boots in a hybrid sector mode. Switch to uniform sector mode on boot. Use the default 20 dummy cycles for a read fast command. The SFDP programming on some older versions of the flash was incorrect. Fixes for that are included in the fixup hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-25 19:17:28 +00:00
{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt. These devices have the same functionality as s28hs512t. In spi-nor-core, use device ID byte to detect S28 family instead of device name. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-08-25 07:48:48 +00:00
{ INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
mtd: spi-nor-core: Add support for Cypress Semper flash The Cypress Semper flash is an xSPI compliant octal DTR flash. Add support for using it in octal DTR mode. The flash by default boots in a hybrid sector mode. Switch to uniform sector mode on boot. Use the default 20 dummy cycles for a read fast command. The SFDP programming on some older versions of the flash was incorrect. Fixes for that are included in the fixup hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-25 19:17:28 +00:00
#endif
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
{ INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
{ INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
{ INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
{ INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
{ INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
{ INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
{ INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
{ INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
{ INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
mtd: spi-nor: enable protection ops for SST26 flash series Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) performs switch from previous 'spi_flash' infrastructure without proper testing/investigations which results in a regressions for SST26 flash series. Enable protection ops for SST26 flash series which were previously enabled by Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs protection ops) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-09 19:33:15 +00:00
{ INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) },
mtd: spi-nor: enable protection ops for SST26 flash series Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) performs switch from previous 'spi_flash' infrastructure without proper testing/investigations which results in a regressions for SST26 flash series. Enable protection ops for SST26 flash series which were previously enabled by Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs protection ops) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-09 19:33:15 +00:00
{ INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
{ INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
{ INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
stm32mp1: fix reference for STMicroelectronics Replace reference to the correct name STMicroelectronics Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-20 16:38:10 +00:00
/* STMicroelectronics -- newer production may have feature updates */
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) },
{ INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) },
{ INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) },
{ INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) },
{ INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) },
{ INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) },
{ INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) },
{ INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) },
{ INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) },
{ INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) },
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
{ INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) },
{ INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) },
{ INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) },
{ INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) },
{ INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
{
INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{ INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{
INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{
INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{
INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{
INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: add Winbond W25Q32JW-IM flash The Kontron SMARC-sAL28 board uses that flash. This is the same change as in the linux commit f3418718c0ec ("mtd: spi-nor: Add support for w25q32jwm"). Signed-off-by: Michael Walle <michael@walle.cc> Reported-by: Leo Krueger <leo.krueger@zal.aero>
2020-11-30 23:12:39 +00:00
{
INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
{
INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add Winbond W25Q128JW ID Add ID for Winbond W25Q128JW device. This is a 128 Mbit QSPI NOR. Tested on W25Q128JWPIM part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-04-24 21:39:17 +00:00
{
INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{
INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{
INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: add winbond w25q512nw family support Add Winbond w25q512nwq/n and w25q512nwm support. datasheet: https://www.winbond.com/resource-files/W25Q512NW%20RevB%2007192021.pdf Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-07-08 19:03:19 +00:00
{
INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add Winbond W25Q512JVQ ID Add ID for Winbond W25Q512JVQ device which is supported on AST2600 EVB by default. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-08-19 09:01:15 +00:00
{
INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi-nor-ids: Add support for W25Q01JV Adds support for Winbond's new 128MB spi nor flash. datasheet: https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevC%2005032021%20Plus%20dummy.pdf Signed-off-by: Ram Narayanan <ramnara@linux.microsoft.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-11-30 05:54:58 +00:00
{
INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support of flash protection to w25q128 The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents various models. From Winbond's website, I could only find 3 types of them: W25Q128JV-IQ/JQ datasheet:https://www.winbond.com/resource-files/ w25q128jv%20revg%2004082019%20plus.pdf W25Q128FV (SPI Mode) datasheet: https://www.winbond.com/resource-files/ w25q128fv%20rev.m%2005132016%20kms.pdf W25Q128BV datesheet: https://www.winbond.com/resource-files/ w25q128bv_revh_100313_wo_automotive.pdf According to the datasheets, all of these 3 types support BP(0,1,2) and TB bits in the status register (SR), so it could reuse the flash protection logic for ST Micro. So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB flags to the w25q128 entry of spi_nor_ids table. Signed-off-by: Su Baocheng <baocheng.su@siemens.com> [jagan: remove comments in spi-nor-ids.c] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-01-25 02:59:05 +00:00
{ INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add Winbond W25M512JW flash entry Add Winbond W25M512JW flash device description. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-09-29 10:04:02 +00:00
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add Winbond W25M512JV flash entry Add Winbond W25M512JV flash device description. Linux already has the flash entry present. A snippet below: { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...}, Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-09-17 14:50:30 +00:00
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for flashes tested by xilinx Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-25 05:17:12 +00:00
{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_XMC
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add support for XMC XM25QH64C This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA smart gateway. Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-17 16:26:51 +00:00
{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi-nor-ids: Add XTX XT25F128B Adds support for XT25F128B used on Odroid Go Advance. Unfortunately this chip uses a continuation code which I cannot seem to parse, so there are possibly going to be collisions with chips that use the same manufacturer/ID. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-05 08:26:41 +00:00
#endif
#ifdef CONFIG_SPI_FLASH_XTX
/* XTX Technology (Shenzhen) Limited */
{ INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
mtd: spi: Add lightweight SPI flash stack for SPL Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-05 05:59:25 +00:00
#endif
{ },
};
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