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u-boot/drivers/cache/cache-v5l2.c

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dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
#include <common.h>
#include <command.h>
#include <cache.h>
#include <dm.h>
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-28 17:45:07 +00:00
#include <hang.h>
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-31 03:38:53 +00:00
#include <asm/global_data.h>
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
#include <asm/io.h>
#include <dm/ofnode.h>
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#include <linux/bitops.h>
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
struct l2cache {
volatile u64 configure;
volatile u64 control;
volatile u64 hpm0;
volatile u64 hpm1;
volatile u64 hpm2;
volatile u64 hpm3;
volatile u64 error_status;
volatile u64 ecc_error;
volatile u64 cctl_command0;
volatile u64 cctl_access_line0;
volatile u64 cctl_command1;
volatile u64 cctl_access_line1;
volatile u64 cctl_command2;
volatile u64 cctl_access_line2;
volatile u64 cctl_command3;
volatile u64 cctl_access_line4;
volatile u64 cctl_status;
};
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:46 +00:00
/* Configuration register */
#define MEM_MAP_OFF 20
#define MEM_MAP_MSK BIT(MEM_MAP_OFF)
/* offset of v0 memory map (Gen1) */
static u32 cmd_stride = 0x10;
static u32 status_stride = 0x0;
static u32 status_bit_offset = 0x4;
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
/* Control Register */
#define L2_ENABLE 0x1
/* prefetch */
#define IPREPETCH_OFF 3
#define DPREPETCH_OFF 5
#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
/* tag ram */
#define TRAMOCTL_OFF 8
#define TRAMICTL_OFF 10
#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
/* data ram */
#define DRAMOCTL_OFF 11
#define DRAMICTL_OFF 13
#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
/* CCTL Command Register */
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:46 +00:00
#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride))
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
#define L2_WBINVAL_ALL 0x12
/* CCTL Status Register */
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:46 +00:00
#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride))
#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset)))
#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset)))
#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset)))
#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset)))
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
DECLARE_GLOBAL_DATA_PTR;
struct v5l2_plat {
struct l2cache *regs;
u32 iprefetch;
u32 dprefetch;
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-27 15:42:39 +00:00
u32 tram_ctl[2];
u32 dram_ctl[2];
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
};
static int v5l2_enable(struct udevice *dev)
{
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:20 +00:00
struct v5l2_plat *plat = dev_get_plat(dev);
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
volatile struct l2cache *regs = plat->regs;
if (regs)
setbits_le32(&regs->control, L2_ENABLE);
return 0;
}
static int v5l2_disable(struct udevice *dev)
{
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:20 +00:00
struct v5l2_plat *plat = dev_get_plat(dev);
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
volatile struct l2cache *regs = plat->regs;
u8 hart = gd->arch.boot_hart;
void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
writel(L2_WBINVAL_ALL, cctlcmd);
while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
printf("L2 flush illegal! hanging...");
hang();
}
}
clrbits_le32(&regs->control, L2_ENABLE);
}
return 0;
}
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:21 +00:00
static int v5l2_of_to_plat(struct udevice *dev)
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
{
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:20 +00:00
struct v5l2_plat *plat = dev_get_plat(dev);
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
struct l2cache *regs;
driver: cache-v5l2: Fix type casting warning on RV32 This patch fixes following warning for the riscv32 toolchain. drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^ Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-06 08:10:53 +00:00
regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev);
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
plat->regs = regs;
plat->iprefetch = -EINVAL;
plat->dprefetch = -EINVAL;
plat->tram_ctl[0] = -EINVAL;
plat->dram_ctl[0] = -EINVAL;
/* Instruction and data fetch prefetch depth */
dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
/* Set tag RAM and data RAM setup and output cycle */
dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
return 0;
}
static int v5l2_probe(struct udevice *dev)
{
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:20 +00:00
struct v5l2_plat *plat = dev_get_plat(dev);
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
struct l2cache *regs = plat->regs;
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:46 +00:00
u32 cfg_val, ctl_val;
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:46 +00:00
cfg_val = readl(&regs->configure);
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
ctl_val = readl(&regs->control);
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:46 +00:00
/* If true, v1 memory map (Gen2) */
if (cfg_val & MEM_MAP_MSK) {
cmd_stride = 0x1000;
status_stride = 0x1000;
status_bit_offset = 0x0;
}
ctl_val |= L2_ENABLE;
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
if (plat->iprefetch != -EINVAL) {
ctl_val &= ~(IPREPETCH_MSK);
ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
}
if (plat->dprefetch != -EINVAL) {
ctl_val &= ~(DPREPETCH_MSK);
ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
}
if (plat->tram_ctl[0] != -EINVAL) {
ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
}
if (plat->dram_ctl[0] != -EINVAL) {
ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
}
writel(ctl_val, &regs->control);
return 0;
}
static const struct udevice_id v5l2_cache_ids[] = {
riscv: ae350: dts: Update L2 cache compatible string Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-06 08:10:48 +00:00
{ .compatible = "cache" },
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
{}
};
static const struct cache_ops v5l2_cache_ops = {
.enable = v5l2_enable,
.disable = v5l2_disable,
};
U_BOOT_DRIVER(v5l2_cache) = {
.name = "v5l2_cache",
.id = UCLASS_CACHE,
.of_match = v5l2_cache_ids,
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:21 +00:00
.of_to_plat = v5l2_of_to_plat,
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
.probe = v5l2_probe,
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:18 +00:00
.plat_auto = sizeof(struct v5l2_plat),
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-28 10:46:06 +00:00
.ops = &v5l2_cache_ops,
.flags = DM_FLAG_PRE_RELOC,
};
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