2014-10-24 20:20:44 +00:00
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if ARCH_SUNXI
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2015-04-06 18:33:34 +00:00
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# Note only one of these may be selected at a time! But hidden choices are
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# not supported by Kconfig
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config SUNXI_GEN_SUN4I
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bool
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---help---
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Select this for sunxi SoCs which have resets and clocks set up
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as the original A10 (mach-sun4i).
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config SUNXI_GEN_SUN6I
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bool
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|
---help---
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Select this for sunxi SoCs which have sun6i like periphery, like
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separate ahb reset control registers, custom pmic bus, new style
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watchdog, etc.
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2014-10-24 20:20:44 +00:00
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choice
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prompt "Sunxi SoC Variant"
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2014-10-24 20:20:45 +00:00
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config MACH_SUN4I
|
2014-10-24 20:20:44 +00:00
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bool "sun4i (Allwinner A10)"
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select CPU_V7
|
2015-04-06 18:33:34 +00:00
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select SUNXI_GEN_SUN4I
|
2014-10-24 20:20:44 +00:00
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select SUPPORT_SPL
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2014-10-24 20:20:45 +00:00
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config MACH_SUN5I
|
2014-10-24 20:20:44 +00:00
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bool "sun5i (Allwinner A13)"
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select CPU_V7
|
2015-04-06 18:33:34 +00:00
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select SUNXI_GEN_SUN4I
|
2014-10-24 20:20:44 +00:00
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select SUPPORT_SPL
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2014-10-24 20:20:45 +00:00
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config MACH_SUN6I
|
2014-10-24 20:20:44 +00:00
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bool "sun6i (Allwinner A31)"
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select CPU_V7
|
2015-05-28 13:25:32 +00:00
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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2015-04-06 18:33:34 +00:00
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select SUNXI_GEN_SUN6I
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2014-10-25 18:18:10 +00:00
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select SUPPORT_SPL
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2015-05-28 13:25:32 +00:00
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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2014-10-24 20:20:44 +00:00
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2014-10-24 20:20:45 +00:00
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config MACH_SUN7I
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2014-10-24 20:20:44 +00:00
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bool "sun7i (Allwinner A20)"
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select CPU_V7
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2014-11-14 08:34:30 +00:00
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
|
2015-04-06 18:33:34 +00:00
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select SUNXI_GEN_SUN4I
|
2014-10-24 20:20:44 +00:00
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select SUPPORT_SPL
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2014-10-24 18:12:04 +00:00
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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2014-10-24 20:20:44 +00:00
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2015-04-06 18:55:39 +00:00
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config MACH_SUN8I_A23
|
2014-10-24 20:20:44 +00:00
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bool "sun8i (Allwinner A23)"
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select CPU_V7
|
2015-05-28 13:25:34 +00:00
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
|
2015-04-06 18:33:34 +00:00
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select SUNXI_GEN_SUN6I
|
2014-12-07 13:34:27 +00:00
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select SUPPORT_SPL
|
2015-05-28 13:25:34 +00:00
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
|
2014-10-24 20:20:44 +00:00
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2015-03-01 18:17:48 +00:00
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config MACH_SUN8I_A33
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bool "sun8i (Allwinner A33)"
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select CPU_V7
|
2015-05-28 13:25:34 +00:00
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
|
2015-03-01 18:17:48 +00:00
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
|
2015-05-28 13:25:34 +00:00
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
|
2015-03-01 18:17:48 +00:00
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2016-05-02 02:28:07 +00:00
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config MACH_SUN8I_A83T
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bool "sun8i (Allwinner A83T)"
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select CPU_V7
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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|
2015-11-17 14:12:58 +00:00
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config MACH_SUN8I_H3
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bool "sun8i (Allwinner H3)"
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select CPU_V7
|
2016-01-06 07:13:09 +00:00
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
|
2015-11-17 14:12:58 +00:00
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select SUNXI_GEN_SUN6I
|
2015-11-17 14:12:59 +00:00
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select SUPPORT_SPL
|
2016-01-06 07:13:09 +00:00
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
|
2015-11-17 14:12:58 +00:00
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|
2015-01-13 18:25:06 +00:00
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config MACH_SUN9I
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bool "sun9i (Allwinner A80)"
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select CPU_V7
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select SUNXI_GEN_SUN6I
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2016-05-02 02:28:07 +00:00
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config MACH_SUN50I
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bool "sun50i (Allwinner A64)"
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select ARM64
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select SUNXI_GEN_SUN6I
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2014-10-24 20:20:44 +00:00
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endchoice
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2014-10-03 12:16:29 +00:00
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2015-04-06 18:55:39 +00:00
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# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
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config MACH_SUN8I
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bool
|
2015-11-28 17:07:19 +00:00
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default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
|
2015-04-06 18:55:39 +00:00
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|
2016-01-11 17:20:58 +00:00
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config DRAM_TYPE
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int "sunxi dram type"
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depends on MACH_SUN8I_A83T
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default 3
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---help---
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Set the dram type, 3: DDR3, 7: LPDDR3
|
2015-04-06 18:55:39 +00:00
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|
2014-11-15 18:46:39 +00:00
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config DRAM_CLK
|
2015-01-17 13:24:55 +00:00
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int "sunxi dram clock speed"
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default 312 if MACH_SUN6I || MACH_SUN8I
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default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
|
2014-11-15 18:46:39 +00:00
|
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|
---help---
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Set the dram clock speed, valid range 240 - 480, must be a multiple
|
2015-01-25 10:29:27 +00:00
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of 24.
|
2014-11-15 18:46:39 +00:00
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|
2015-01-31 22:27:06 +00:00
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if MACH_SUN5I || MACH_SUN7I
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config DRAM_MBUS_CLK
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int "sunxi mbus clock speed"
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default 300
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---help---
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|
Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
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endif
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|
2014-11-15 18:46:39 +00:00
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config DRAM_ZQ
|
2015-01-17 13:24:55 +00:00
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int "sunxi dram zq value"
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default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
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default 127 if MACH_SUN7I
|
2014-11-15 18:46:39 +00:00
|
|
|
---help---
|
2015-01-25 10:29:27 +00:00
|
|
|
Set the dram zq value.
|
2015-01-17 13:24:55 +00:00
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|
|
2015-05-13 13:00:46 +00:00
|
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config DRAM_ODT_EN
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bool "sunxi dram odt enable"
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default n if !MACH_SUN8I_A23
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default y if MACH_SUN8I_A23
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|
|
---help---
|
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|
|
Select this to enable dram odt (on die termination).
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|
2015-01-17 13:24:55 +00:00
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|
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if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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config DRAM_EMR1
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|
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int "sunxi dram emr1 value"
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|
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default 0 if MACH_SUN4I
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|
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default 4 if MACH_SUN5I || MACH_SUN7I
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|
|
---help---
|
2015-01-25 10:29:27 +00:00
|
|
|
Set the dram controller emr1 value.
|
2015-01-31 22:27:05 +00:00
|
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|
2015-01-31 22:27:06 +00:00
|
|
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config DRAM_TPR3
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|
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hex "sunxi dram tpr3 value"
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|
|
default 0
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|
|
|
---help---
|
|
|
|
Set the dram controller tpr3 parameter. This parameter configures
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|
|
the delay on the command lane and also phase shifts, which are
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|
|
applied for sampling incoming read data. The default value 0
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|
|
means that no phase/delay adjustments are necessary. Properly
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|
|
configuring this parameter increases reliability at high DRAM
|
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|
|
clock speeds.
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config DRAM_DQS_GATING_DELAY
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|
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hex "sunxi dram dqs_gating_delay value"
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|
|
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default 0
|
|
|
|
---help---
|
|
|
|
Set the dram controller dqs_gating_delay parmeter. Each byte
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|
|
encodes the DQS gating delay for each byte lane. The delay
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|
|
granularity is 1/4 cycle. For example, the value 0x05060606
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|
|
|
means that the delay is 5 quarter-cycles for one lane (1.25
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|
|
|
cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
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|
|
|
The default value 0 means autodetection. The results of hardware
|
|
|
|
autodetection are not very reliable and depend on the chip
|
|
|
|
temperature (sometimes producing different results on cold start
|
|
|
|
and warm reboot). But the accuracy of hardware autodetection
|
|
|
|
is usually good enough, unless running at really high DRAM
|
|
|
|
clocks speeds (up to 600MHz). If unsure, keep as 0.
|
|
|
|
|
2015-01-31 22:27:05 +00:00
|
|
|
choice
|
|
|
|
prompt "sunxi dram timings"
|
|
|
|
default DRAM_TIMINGS_VENDOR_MAGIC
|
|
|
|
---help---
|
|
|
|
Select the timings of the DDR3 chips.
|
|
|
|
|
|
|
|
config DRAM_TIMINGS_VENDOR_MAGIC
|
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|
|
bool "Magic vendor timings from Android"
|
|
|
|
---help---
|
|
|
|
The same DRAM timings as in the Allwinner boot0 bootloader.
|
|
|
|
|
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|
|
config DRAM_TIMINGS_DDR3_1066F_1333H
|
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|
|
bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
|
|
|
|
---help---
|
|
|
|
Use the timings of the standard JEDEC DDR3-1066F speed bin for
|
|
|
|
DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
|
|
|
|
for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
|
|
|
|
used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
|
|
|
|
or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
|
|
|
|
that down binning to DDR3-1066F is supported (because DDR3-1066F
|
|
|
|
uses a bit faster timings than DDR3-1333H).
|
|
|
|
|
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|
|
config DRAM_TIMINGS_DDR3_800E_1066G_1333J
|
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|
|
bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
|
|
|
|
---help---
|
|
|
|
Use the timings of the slowest possible JEDEC speed bin for the
|
|
|
|
selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
|
|
|
|
DDR3-800E, DDR3-1066G or DDR3-1333J.
|
|
|
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|
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|
|
endchoice
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|
2014-11-15 18:46:39 +00:00
|
|
|
endif
|
|
|
|
|
2015-05-13 13:00:46 +00:00
|
|
|
if MACH_SUN8I_A23
|
|
|
|
config DRAM_ODT_CORRECTION
|
|
|
|
int "sunxi dram odt correction value"
|
|
|
|
default 0
|
|
|
|
---help---
|
|
|
|
Set the dram odt correction value (range -255 - 255). In allwinner
|
|
|
|
fex files, this option is found in bits 8-15 of the u32 odt_en variable
|
|
|
|
in the [dram] section. When bit 31 of the odt_en variable is set
|
|
|
|
then the correction is negative. Usually the value for this is 0.
|
|
|
|
endif
|
|
|
|
|
2015-03-28 10:26:38 +00:00
|
|
|
config SYS_CLK_FREQ
|
2016-03-29 15:29:10 +00:00
|
|
|
default 816000000 if MACH_SUN50I
|
2015-03-28 10:26:38 +00:00
|
|
|
default 912000000 if MACH_SUN7I
|
|
|
|
default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
|
|
|
|
|
2014-10-03 12:16:29 +00:00
|
|
|
config SYS_CONFIG_NAME
|
2014-10-24 20:20:45 +00:00
|
|
|
default "sun4i" if MACH_SUN4I
|
|
|
|
default "sun5i" if MACH_SUN5I
|
|
|
|
default "sun6i" if MACH_SUN6I
|
|
|
|
default "sun7i" if MACH_SUN7I
|
|
|
|
default "sun8i" if MACH_SUN8I
|
2015-01-13 18:25:06 +00:00
|
|
|
default "sun9i" if MACH_SUN9I
|
2016-03-29 15:29:10 +00:00
|
|
|
default "sun50i" if MACH_SUN50I
|
2014-07-30 05:08:14 +00:00
|
|
|
|
|
|
|
config SYS_BOARD
|
|
|
|
default "sunxi"
|
|
|
|
|
|
|
|
config SYS_SOC
|
|
|
|
default "sunxi"
|
|
|
|
|
2014-12-25 00:34:47 +00:00
|
|
|
config UART0_PORT_F
|
|
|
|
bool "UART0 on MicroSD breakout board"
|
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Repurpose the SD card slot for getting access to the UART0 serial
|
|
|
|
console. Primarily useful only for low level u-boot debugging on
|
|
|
|
tablets, where normal UART0 is difficult to access and requires
|
|
|
|
device disassembly and/or soldering. As the SD card can't be used
|
|
|
|
at the same time, the system can be only booted in the FEL mode.
|
|
|
|
Only enable this if you really know what you are doing.
|
|
|
|
|
2014-10-22 12:56:36 +00:00
|
|
|
config OLD_SUNXI_KERNEL_COMPAT
|
|
|
|
boolean "Enable workarounds for booting old kernels"
|
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Set this to enable various workarounds for old kernels, this results in
|
|
|
|
sub-optimal settings for newer kernels, only enable if needed.
|
|
|
|
|
2015-10-15 20:04:07 +00:00
|
|
|
config MMC
|
|
|
|
depends on !UART0_PORT_F
|
|
|
|
default y if ARCH_SUNXI
|
|
|
|
|
2014-10-02 18:29:26 +00:00
|
|
|
config MMC0_CD_PIN
|
|
|
|
string "Card detect pin for mmc0"
|
2016-05-02 02:28:08 +00:00
|
|
|
default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
|
2014-10-02 18:29:26 +00:00
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the card detect pin for mmc0, leave empty to not use cd. This
|
|
|
|
takes a string in the format understood by sunxi_name_to_gpio, e.g.
|
|
|
|
PH1 for pin 1 of port H.
|
|
|
|
|
|
|
|
config MMC1_CD_PIN
|
|
|
|
string "Card detect pin for mmc1"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
See MMC0_CD_PIN help text.
|
|
|
|
|
|
|
|
config MMC2_CD_PIN
|
|
|
|
string "Card detect pin for mmc2"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
See MMC0_CD_PIN help text.
|
|
|
|
|
|
|
|
config MMC3_CD_PIN
|
|
|
|
string "Card detect pin for mmc3"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
See MMC0_CD_PIN help text.
|
|
|
|
|
2015-03-22 17:12:23 +00:00
|
|
|
config MMC1_PINS
|
|
|
|
string "Pins for mmc1"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the pins used for mmc1, when applicable. This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
|
|
|
|
|
|
|
|
config MMC2_PINS
|
|
|
|
string "Pins for mmc2"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
See MMC1_PINS help text.
|
|
|
|
|
|
|
|
config MMC3_PINS
|
|
|
|
string "Pins for mmc3"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
See MMC1_PINS help text.
|
|
|
|
|
2014-10-02 18:43:50 +00:00
|
|
|
config MMC_SUNXI_SLOT_EXTRA
|
|
|
|
int "mmc extra slot number"
|
|
|
|
default -1
|
|
|
|
---help---
|
|
|
|
sunxi builds always enable mmc0, some boards also have a second sdcard
|
|
|
|
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
|
|
|
|
support for this.
|
|
|
|
|
2016-04-01 20:39:26 +00:00
|
|
|
config INITIAL_USB_SCAN_DELAY
|
|
|
|
int "delay initial usb scan by x ms to allow builtin devices to init"
|
|
|
|
default 0
|
|
|
|
---help---
|
|
|
|
Some boards have on board usb devices which need longer than the
|
|
|
|
USB spec's 1 second to connect from board powerup. Set this config
|
|
|
|
option to a non 0 value to add an extra delay before the first usb
|
|
|
|
bus scan.
|
|
|
|
|
2015-01-07 14:26:06 +00:00
|
|
|
config USB0_VBUS_PIN
|
|
|
|
string "Vbus enable pin for usb0 (otg)"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the Vbus enable pin for usb0 (otg). This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2015-02-16 21:13:43 +00:00
|
|
|
config USB0_VBUS_DET
|
|
|
|
string "Vbus detect pin for usb0 (otg)"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the Vbus detect pin for usb0 (otg). This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2015-06-14 15:29:53 +00:00
|
|
|
config USB0_ID_DET
|
|
|
|
string "ID detect pin for usb0 (otg)"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the ID detect pin for usb0 (otg). This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2014-11-07 15:09:00 +00:00
|
|
|
config USB1_VBUS_PIN
|
|
|
|
string "Vbus enable pin for usb1 (ehci0)"
|
|
|
|
default "PH6" if MACH_SUN4I || MACH_SUN7I
|
2014-11-07 13:51:12 +00:00
|
|
|
default "PH27" if MACH_SUN6I
|
2014-11-07 15:09:00 +00:00
|
|
|
---help---
|
|
|
|
Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
|
|
|
|
a string in the format understood by sunxi_name_to_gpio, e.g.
|
|
|
|
PH1 for pin 1 of port H.
|
|
|
|
|
|
|
|
config USB2_VBUS_PIN
|
|
|
|
string "Vbus enable pin for usb2 (ehci1)"
|
|
|
|
default "PH3" if MACH_SUN4I || MACH_SUN7I
|
2014-11-07 13:51:12 +00:00
|
|
|
default "PH24" if MACH_SUN6I
|
2014-11-07 15:09:00 +00:00
|
|
|
---help---
|
|
|
|
See USB1_VBUS_PIN help text.
|
|
|
|
|
2016-03-18 07:42:01 +00:00
|
|
|
config USB3_VBUS_PIN
|
|
|
|
string "Vbus enable pin for usb3 (ehci2)"
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
See USB1_VBUS_PIN help text.
|
|
|
|
|
2015-04-10 21:09:52 +00:00
|
|
|
config I2C0_ENABLE
|
|
|
|
bool "Enable I2C/TWI controller 0"
|
|
|
|
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
|
|
|
|
default n if MACH_SUN6I || MACH_SUN8I
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2015-04-10 21:09:52 +00:00
|
|
|
---help---
|
|
|
|
This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
|
|
|
|
its clock and setting up the bus. This is especially useful on devices
|
|
|
|
with slaves connected to the bus or with pins exposed through e.g. an
|
|
|
|
expansion port/header.
|
|
|
|
|
|
|
|
config I2C1_ENABLE
|
|
|
|
bool "Enable I2C/TWI controller 1"
|
|
|
|
default n
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2015-04-10 21:09:52 +00:00
|
|
|
---help---
|
|
|
|
See I2C0_ENABLE help text.
|
|
|
|
|
|
|
|
config I2C2_ENABLE
|
|
|
|
bool "Enable I2C/TWI controller 2"
|
|
|
|
default n
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2015-04-10 21:09:52 +00:00
|
|
|
---help---
|
|
|
|
See I2C0_ENABLE help text.
|
|
|
|
|
|
|
|
if MACH_SUN6I || MACH_SUN7I
|
|
|
|
config I2C3_ENABLE
|
|
|
|
bool "Enable I2C/TWI controller 3"
|
|
|
|
default n
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2015-04-10 21:09:52 +00:00
|
|
|
---help---
|
|
|
|
See I2C0_ENABLE help text.
|
|
|
|
endif
|
|
|
|
|
2016-02-23 17:47:19 +00:00
|
|
|
if SUNXI_GEN_SUN6I
|
2016-01-14 13:06:26 +00:00
|
|
|
config R_I2C_ENABLE
|
|
|
|
bool "Enable the PRCM I2C/TWI controller"
|
2016-02-23 17:47:19 +00:00
|
|
|
# This is used for the pmic on H3
|
|
|
|
default y if SY8106A_POWER
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2016-01-14 13:06:26 +00:00
|
|
|
---help---
|
|
|
|
Set this to y to enable the I2C controller which is part of the PRCM.
|
2016-02-23 17:47:19 +00:00
|
|
|
endif
|
2016-01-14 13:06:26 +00:00
|
|
|
|
2015-04-10 21:09:52 +00:00
|
|
|
if MACH_SUN7I
|
|
|
|
config I2C4_ENABLE
|
|
|
|
bool "Enable I2C/TWI controller 4"
|
|
|
|
default n
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2015-04-10 21:09:52 +00:00
|
|
|
---help---
|
|
|
|
See I2C0_ENABLE help text.
|
|
|
|
endif
|
|
|
|
|
2015-04-25 15:25:14 +00:00
|
|
|
config AXP_GPIO
|
|
|
|
boolean "Enable support for gpio-s on axp PMICs"
|
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
config VIDEO
|
2014-12-21 15:28:32 +00:00
|
|
|
boolean "Enable graphical uboot console on HDMI, LCD or VGA"
|
2016-05-02 02:28:09 +00:00
|
|
|
depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64
|
2014-08-13 05:55:06 +00:00
|
|
|
default y
|
|
|
|
---help---
|
2014-12-21 15:28:32 +00:00
|
|
|
Say Y here to add support for using a cfb console on the HDMI, LCD
|
|
|
|
or VGA output found on most sunxi devices. See doc/README.video for
|
|
|
|
info on how to select the video output and mode.
|
|
|
|
|
2014-12-23 22:04:35 +00:00
|
|
|
config VIDEO_HDMI
|
|
|
|
boolean "HDMI output support"
|
|
|
|
depends on VIDEO && !MACH_SUN8I
|
|
|
|
default y
|
|
|
|
---help---
|
|
|
|
Say Y here to add support for outputting video over HDMI.
|
|
|
|
|
2014-12-25 12:58:06 +00:00
|
|
|
config VIDEO_VGA
|
|
|
|
boolean "VGA output support"
|
|
|
|
depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
|
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Say Y here to add support for outputting video over VGA.
|
|
|
|
|
2014-12-24 11:17:07 +00:00
|
|
|
config VIDEO_VGA_VIA_LCD
|
|
|
|
boolean "VGA via LCD controller support"
|
2015-01-12 10:02:10 +00:00
|
|
|
depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
|
2014-12-24 11:17:07 +00:00
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Say Y here to add support for external DACs connected to the parallel
|
|
|
|
LCD interface driving a VGA connector, such as found on the
|
|
|
|
Olimex A13 boards.
|
|
|
|
|
2015-01-25 14:33:07 +00:00
|
|
|
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
|
|
|
|
boolean "Force sync active high for VGA via LCD controller support"
|
|
|
|
depends on VIDEO_VGA_VIA_LCD
|
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Say Y here if you've a board which uses opendrain drivers for the vga
|
|
|
|
hsync and vsync signals. Opendrain drivers cannot generate steep enough
|
|
|
|
positive edges for a stable video output, so on boards with opendrain
|
|
|
|
drivers the sync signals must always be active high.
|
|
|
|
|
2015-01-12 10:02:11 +00:00
|
|
|
config VIDEO_VGA_EXTERNAL_DAC_EN
|
|
|
|
string "LCD panel power enable pin"
|
|
|
|
depends on VIDEO_VGA_VIA_LCD
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the enable pin for the external VGA DAC. This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2015-08-03 17:20:26 +00:00
|
|
|
config VIDEO_COMPOSITE
|
|
|
|
boolean "Composite video output support"
|
|
|
|
depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
|
|
|
|
default n
|
|
|
|
---help---
|
|
|
|
Say Y here to add support for outputting composite video.
|
|
|
|
|
2014-12-21 15:28:32 +00:00
|
|
|
config VIDEO_LCD_MODE
|
|
|
|
string "LCD panel timing details"
|
|
|
|
depends on VIDEO
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
LCD panel timing details string, leave empty if there is no LCD panel.
|
|
|
|
This is in drivers/video/videomodes.c: video_get_params() format, e.g.
|
|
|
|
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
|
2015-08-16 09:23:42 +00:00
|
|
|
Also see: http://linux-sunxi.org/LCD
|
2014-12-21 15:28:32 +00:00
|
|
|
|
2015-01-13 12:21:46 +00:00
|
|
|
config VIDEO_LCD_DCLK_PHASE
|
|
|
|
int "LCD panel display clock phase"
|
|
|
|
depends on VIDEO
|
|
|
|
default 1
|
|
|
|
---help---
|
|
|
|
Select LCD panel display clock phase shift, range 0-3.
|
|
|
|
|
2014-12-21 15:28:32 +00:00
|
|
|
config VIDEO_LCD_POWER
|
|
|
|
string "LCD panel power enable pin"
|
|
|
|
depends on VIDEO
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the power enable pin for the LCD panel. This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2015-02-16 16:26:41 +00:00
|
|
|
config VIDEO_LCD_RESET
|
|
|
|
string "LCD panel reset pin"
|
|
|
|
depends on VIDEO
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the reset pin for the LCD panel. This takes a string in the format
|
|
|
|
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2014-12-21 15:28:32 +00:00
|
|
|
config VIDEO_LCD_BL_EN
|
|
|
|
string "LCD panel backlight enable pin"
|
|
|
|
depends on VIDEO
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the backlight enable pin for the LCD panel. This takes a string in the
|
|
|
|
the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
|
|
|
|
port H.
|
|
|
|
|
|
|
|
config VIDEO_LCD_BL_PWM
|
|
|
|
string "LCD panel backlight pwm pin"
|
|
|
|
depends on VIDEO
|
|
|
|
default ""
|
|
|
|
---help---
|
|
|
|
Set the backlight pwm pin for the LCD panel. This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2015-01-22 20:02:42 +00:00
|
|
|
config VIDEO_LCD_BL_PWM_ACTIVE_LOW
|
|
|
|
bool "LCD panel backlight pwm is inverted"
|
|
|
|
depends on VIDEO
|
|
|
|
default y
|
|
|
|
---help---
|
|
|
|
Set this if the backlight pwm output is active low.
|
|
|
|
|
2015-02-16 16:23:25 +00:00
|
|
|
config VIDEO_LCD_PANEL_I2C
|
|
|
|
bool "LCD panel needs to be configured via i2c"
|
|
|
|
depends on VIDEO
|
2015-03-07 11:00:02 +00:00
|
|
|
default n
|
2016-05-15 11:51:58 +00:00
|
|
|
select CMD_I2C
|
2015-02-16 16:23:25 +00:00
|
|
|
---help---
|
|
|
|
Say y here if the LCD panel needs to be configured via i2c. This
|
|
|
|
will add a bitbang i2c controller using gpios to talk to the LCD.
|
|
|
|
|
|
|
|
config VIDEO_LCD_PANEL_I2C_SDA
|
|
|
|
string "LCD panel i2c interface SDA pin"
|
|
|
|
depends on VIDEO_LCD_PANEL_I2C
|
|
|
|
default "PG12"
|
|
|
|
---help---
|
|
|
|
Set the SDA pin for the LCD i2c interface. This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
|
|
|
config VIDEO_LCD_PANEL_I2C_SCL
|
|
|
|
string "LCD panel i2c interface SCL pin"
|
|
|
|
depends on VIDEO_LCD_PANEL_I2C
|
|
|
|
default "PG10"
|
|
|
|
---help---
|
|
|
|
Set the SCL pin for the LCD i2c interface. This takes a string in the
|
|
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
2015-01-01 21:04:34 +00:00
|
|
|
|
|
|
|
# Note only one of these may be selected at a time! But hidden choices are
|
|
|
|
# not supported by Kconfig
|
|
|
|
config VIDEO_LCD_IF_PARALLEL
|
|
|
|
bool
|
|
|
|
|
|
|
|
config VIDEO_LCD_IF_LVDS
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
|
|
choice
|
|
|
|
prompt "LCD panel support"
|
|
|
|
depends on VIDEO
|
|
|
|
---help---
|
|
|
|
Select which type of LCD panel to support.
|
|
|
|
|
|
|
|
config VIDEO_LCD_PANEL_PARALLEL
|
|
|
|
bool "Generic parallel interface LCD panel"
|
|
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
|
|
|
|
|
|
config VIDEO_LCD_PANEL_LVDS
|
|
|
|
bool "Generic lvds interface LCD panel"
|
|
|
|
select VIDEO_LCD_IF_LVDS
|
|
|
|
|
2015-01-19 03:23:33 +00:00
|
|
|
config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
|
|
|
|
bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
|
|
|
|
select VIDEO_LCD_SSD2828
|
|
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
|
|
---help---
|
2015-08-08 14:13:53 +00:00
|
|
|
7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
|
|
|
|
|
|
|
|
config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
|
|
|
|
bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
|
|
|
|
select VIDEO_LCD_ANX9804
|
|
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
|
|
select VIDEO_LCD_PANEL_I2C
|
|
|
|
---help---
|
|
|
|
Select this for eDP LCD panels with 4 lanes running at 1.62G,
|
|
|
|
connected via an ANX9804 bridge chip.
|
2015-01-19 03:23:33 +00:00
|
|
|
|
2015-01-20 08:23:36 +00:00
|
|
|
config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
|
|
|
|
bool "Hitachi tx18d42vm LCD panel"
|
|
|
|
select VIDEO_LCD_HITACHI_TX18D42VM
|
|
|
|
select VIDEO_LCD_IF_LVDS
|
|
|
|
---help---
|
|
|
|
7.85" 1024x768 Hitachi tx18d42vm LCD panel support
|
|
|
|
|
2015-02-16 16:49:47 +00:00
|
|
|
config VIDEO_LCD_TL059WV5C0
|
|
|
|
bool "tl059wv5c0 LCD panel"
|
|
|
|
select VIDEO_LCD_PANEL_I2C
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select VIDEO_LCD_IF_PARALLEL
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---help---
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6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
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Aigo M60/M608/M606 tablets.
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2015-01-01 21:04:34 +00:00
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endchoice
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2015-01-25 11:10:48 +00:00
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config GMAC_TX_DELAY
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|
|
int "GMAC Transmit Clock Delay Chain"
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|
default 0
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|
|
---help---
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|
|
Set the GMAC Transmit Clock Delay Chain value.
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|
2015-09-13 11:02:48 +00:00
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|
|
config SPL_STACK_R_ADDR
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2016-03-29 15:29:10 +00:00
|
|
|
default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
|
2015-09-13 11:02:48 +00:00
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|
|
default 0x2fe00000 if MACH_SUN9I
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|
|
|
|
2014-07-30 05:08:14 +00:00
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|
|
endif
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