2018-06-14 18:08:32 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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2020-04-19 13:58:25 +00:00
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* Actions Semi Owl SoCs platform support.
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2018-06-14 18:08:32 +00:00
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*
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* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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2019-12-28 17:45:01 +00:00
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#include <cpu_func.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2020-05-10 17:39:56 +00:00
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#include <asm/cache.h>
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2018-06-14 18:08:32 +00:00
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#include <linux/arm-smccc.h>
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#include <linux/psci.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/psci.h>
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2020-05-09 08:15:07 +00:00
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#define DMM_INTERLEAVE_PER_CH_CFG 0xe0290028
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2018-06-14 18:08:32 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2020-05-09 08:15:07 +00:00
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unsigned int owl_get_ddrcap(void)
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{
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unsigned int val, cap;
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/* ddr capacity register initialized by ddr driver
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* in early bootloader
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*/
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#if defined(CONFIG_MACH_S700)
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val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7;
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cap = (val + 1) * 256;
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#elif defined(CONFIG_MACH_S900)
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val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0xf;
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cap = 64 * (1 << val);
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#endif
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return cap;
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}
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2018-06-14 18:08:32 +00:00
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/*
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* dram_init - sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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2020-05-09 08:15:07 +00:00
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gd->ram_size = owl_get_ddrcap() * 1024 * 1024;
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2018-06-14 18:08:32 +00:00
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return 0;
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}
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/* This is called after dram_init() so use get_ram_size result */
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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static void show_psci_version(void)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
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printf("PSCI: v%ld.%ld\n",
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2020-04-19 13:58:25 +00:00
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PSCI_VERSION_MAJOR(res.a0),
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2018-06-14 18:08:32 +00:00
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PSCI_VERSION_MINOR(res.a0));
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}
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int board_init(void)
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{
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show_psci_version();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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