Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-13 14:53:06 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/board/samtec/vining_2000/imximage.cfg

132 lines
2.8 KiB
INI
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
mx6sx: Add initial support for Samtec VIN|ING 2000 board This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
2016-11-29 15:13:40 +00:00
/*
* Copyright (C) 2016 samtec automotive software & electronics gmbh
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
/* IOMUX - DDR IO Type */
DATA 4 0x020e0618 0x000c0000
DATA 4 0x020e05fc 0x00000000
/* Clock */
DATA 4 0x020e032c 0x00000030
/* Address */
DATA 4 0x020e0300 0x00000028
DATA 4 0x020e02fc 0x00000028
DATA 4 0x020e05f4 0x00000028
/* Control */
DATA 4 0x020e0340 0x00000028
DATA 4 0x020e0320 0x00000000
DATA 4 0x020e0310 0x00000028
DATA 4 0x020e0314 0x00000028
DATA 4 0x020e0614 0x00000028
/* Data Strobe */
DATA 4 0x020e05f8 0x00020000
DATA 4 0x020e0330 0x00000028
DATA 4 0x020e0334 0x00000028
DATA 4 0x020e0338 0x00000028
DATA 4 0x020e033c 0x00000028
/* Data */
DATA 4 0x020e0608 0x00020000
DATA 4 0x020e060c 0x00000028
DATA 4 0x020e0610 0x00000028
DATA 4 0x020e061c 0x00000028
DATA 4 0x020e0620 0x00000028
DATA 4 0x020e02ec 0x00000028
DATA 4 0x020e02f0 0x00000028
DATA 4 0x020e02f4 0x00000028
DATA 4 0x020e02f8 0x00000028
/* Calibrations - ZQ */
DATA 4 0x021b0800 0xa1390003
/* Write leveling */
DATA 4 0x021b080c 0x00290025
DATA 4 0x021b0810 0x00210022
/* DQS Read Gate */
DATA 4 0x021b083c 0x4142013a
DATA 4 0x021b0840 0x012e0123
/* Read/Write Delay */
DATA 4 0x021b0848 0x43474949
DATA 4 0x021b0850 0x38383c38
/* Read data bit delay */
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
/* Complete calibration by forced measurement */
DATA 4 0x021b08b8 0x00000800
/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4 0x021b0004 0x0002002d
DATA 4 0x021b0008 0x00333040
DATA 4 0x021b000c 0x676b52f2
DATA 4 0x021b0010 0x926e8b63
DATA 4 0x021b0014 0x01ff00db
DATA 4 0x021b0018 0x00011740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x006b1023
DATA 4 0x021b0040 0x0000005f
DATA 4 0x021b0000 0x84190000
/* Initialize MT41K256M16HA-125 - MR2 */
DATA 4 0x021b001c 0x02008032
/* MR3 */
DATA 4 0x021b001c 0x00008033
/* MR1 */
DATA 4 0x021b001c 0x00048031
/* MR0 */
DATA 4 0x021b001c 0x15108030
/* DDR device ZQ calibration */
DATA 4 0x021b001c 0x04008040
/* Final DDR setup, before operation start */
DATA 4 0x021b0020 0x00007800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b001c 0x00000000
Reference in a new issue Copy permalink