2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-04-26 00:25:23 +00:00
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
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#ifndef __FTAHBC020S_H
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#define __FTAHBC202S_H
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/* Registers Offsets */
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/*
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* AHB Slave BSR, offset: n * 4, n=0~31
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*/
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#ifndef __ASSEMBLY__
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struct ftahbc02s {
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unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */
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unsigned int pcr; /* 0x80 - Priority Ctrl Reg */
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unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */
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unsigned int cr; /* 0x88 - Ctrl Reg */
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};
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#endif /* __ASSEMBLY__ */
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/*
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* FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
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*/
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#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20)
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#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16)
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/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
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#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */
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/*
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* FTAHBC020S_PCR - Priority Control Register
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*/
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#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */
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/*
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* FTAHBC020S_CR - Interrupt Control Register
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*/
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#define FTAHBC020S_CR_INTSTS (1 << 24)
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#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20)
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#define FTAHBC020S_CR_INTSMASK (1 << 16)
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#define FTAHBC020S_CR_REMAP (1 << 0)
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#endif /* __FTAHBC020S_H */
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