mirror of
https://github.com/AsahiLinux/u-boot
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65 lines
1.3 KiB
C
65 lines
1.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <asm/csr.h>
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#include <asm/sections.h>
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#include <dm.h>
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#include <log.h>
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#define CSR_U74_FEATURE_DISABLE 0x7c1
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#define L2_LIM_MEM_END 0x81FFFFFUL
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int spl_soc_init(void)
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{
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int ret;
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struct udevice *dev;
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/* DDR init */
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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void harts_early_init(void)
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{
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ulong *ptr;
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u8 *tmp;
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ulong len, remain;
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/*
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* Feature Disable CSR
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*
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* Clear feature disable CSR to '0' to turn on all features for
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* each core. This operation must be in M-mode.
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*/
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if (CONFIG_IS_ENABLED(RISCV_MMODE))
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csr_write(CSR_U74_FEATURE_DISABLE, 0);
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/* clear L2 LIM memory
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* set __bss_end to 0x81FFFFF region to zero
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* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
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* If it is not cleared, the ECC part is invalid, and an ECC error
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* will be reported when reading data.
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*/
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ptr = (ulong *)&__bss_end;
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len = L2_LIM_MEM_END - (ulong)&__bss_end;
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remain = len % sizeof(ulong);
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len /= sizeof(ulong);
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while (len--)
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*ptr++ = 0;
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/* clear the remain bytes */
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if (remain) {
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tmp = (u8 *)ptr;
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while (remain--)
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*tmp++ = 0;
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}
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}
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