u-boot/arch/arm/dts/socfpga_cyclone5_de10_nano.dts

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, Intel Corporation
*
* based on socfpga_cyclone5_de0_nano_soc.dts
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "Terasic DE10-Nano";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &gmac1;
udc0 = &usb1;
};
memory {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
rxd0-skew-ps = <420>;
rxd1-skew-ps = <420>;
rxd2-skew-ps = <420>;
rxd3-skew-ps = <420>;
txen-skew-ps = <0>;
txc-skew-ps = <1860>;
rxdv-skew-ps = <420>;
rxc-skew-ps = <1680>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&porta {
bank-name = "porta";
};
&portb {
bank-name = "portb";
};
&portc {
bank-name = "portc";
};
&mmc0 {
status = "okay";
u-boot,dm-pre-reloc;
};
&usb1 {
status = "okay";
};
&uart0 {
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
&watchdog0 {
status = "disabled";
};