2015-07-01 04:28:03 +00:00
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/*
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* (C) Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Extracted from gic_64.S
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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/*************************************************************************
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*
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* void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
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* CCI_MN_DVM_DOMAIN_CTL_SET);
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*
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* Add fully-coherent masters to DVM domain
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*
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*************************************************************************/
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ENTRY(ccn504_add_masters_to_dvm)
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/*
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* x0: CCI_MN_BASE
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* x1: CCI_MN_RNF_NODEID_LIST
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* x2: CCI_MN_DVM_DOMAIN_CTL_SET
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*/
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/* Add fully-coherent masters to DVM domain */
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ldr x9, [x0, x1]
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str x9, [x0, x2]
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1: ldr x10, [x0, x2]
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mvn x11, x10
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tst x11, x10 /* Wait for domain addition to complete */
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b.ne 1b
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ret
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ENDPROC(ccn504_add_masters_to_dvm)
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/*************************************************************************
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*
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* void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value);
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*
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* Initialize QoS settings for AR/AW override.
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* Right now, this function sets the same QoS value for all RN-I ports
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*
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*************************************************************************/
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ENTRY(ccn504_set_qos)
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/*
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* x0: CCI_Sx_QOS_CONTROL_BASE
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* x1: QoS Value
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*/
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/* Set all RN-I ports to QoS value denoted by x1 */
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ldr x9, [x0]
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mov x10, x1
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orr x9, x9, x10
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str x9, [x0]
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ret
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ENDPROC(ccn504_set_qos)
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2016-01-25 06:38:45 +00:00
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/*************************************************************************
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*
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* void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value);
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*
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* Initialize AUX control settings
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*
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*************************************************************************/
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ENTRY(ccn504_set_aux)
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/*
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* x0: CCI_AUX_CONTROL_BASE
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* x1: Value
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*/
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ldr x9, [x0]
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mov x10, x1
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orr x9, x9, x10
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str x9, [x0]
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ret
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ENDPROC(ccn504_set_aux)
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