2011-11-01 20:00:35 +00:00
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated
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*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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/* SoC Configuration */
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#define CONFIG_ARM926EJS /* arm926ejs CPU */
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SOC_DM365
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#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
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#define CONFIG_HOSTNAME cam_enc_4xx
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#define BOARD_LATE_INIT
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#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
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/* Memory Info */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
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#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
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#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Serial Driver info: UART0 for console */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 0x01c20000
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* Network Configuration */
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_EMAC_MDIO_PHY_NUM 0
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#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_CMD_MII
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_RESET_PHY_R
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/* I2C */
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
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/* NAND: socketed, two chipselects, normally 2 GBytes */
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NAND_CS 2
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
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/* socket has two chipselects, nCE0 gated by address BIT(14) */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* SPI support */
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_DAVINCI_SPI
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#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
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#define CONFIG_SF_DEFAULT_SPEED 3000000
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#define CONFIG_CMD_SF
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DAVINCI_MMC
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#define CONFIG_MMC_MBLOCK
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/* U-Boot command configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#ifdef CONFIG_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MMC
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_UBI
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2012-01-16 21:20:09 +00:00
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#define CONFIG_CMD_UBIFS
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2011-11-01 20:00:35 +00:00
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#define CONFIG_RBTREE
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2012-01-16 21:20:09 +00:00
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#define CONFIG_LZO
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2011-11-01 20:00:35 +00:00
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#endif
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/* U-Boot general configuration */
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP
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2012-01-16 21:20:09 +00:00
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#define CONFIG_MENU
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#define CONFIG_MENU_SHOW
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#define CONFIG_FIT
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#define CONFIG_CMD_PXE
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#define CONFIG_BOARD_IMG_ADDR_R 0x80000000
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2011-11-01 20:00:35 +00:00
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#ifdef CONFIG_NAND_DAVINCI
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2012-01-16 21:20:09 +00:00
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#define CONFIG_ENV_SIZE (16 << 10)
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2011-11-01 20:00:35 +00:00
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#define CONFIG_ENV_IS_IN_NAND
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2012-01-16 21:20:09 +00:00
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#define CONFIG_ENV_OFFSET 0x180000
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#define CONFIG_ENV_OFFSET_REDUND 0x1c0000
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#define CONFIG_ENV_RANGE 0x020000
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2011-11-01 20:00:35 +00:00
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#undef CONFIG_ENV_IS_IN_FLASH
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#endif
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#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
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#define CONFIG_CMD_ENV
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2012-01-16 21:20:09 +00:00
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#define CONFIG_SYS_MMC_ENV_DEV 0
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2011-11-01 20:00:35 +00:00
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
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#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
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#define CONFIG_ENV_IS_IN_MMC
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#undef CONFIG_ENV_IS_IN_FLASH
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#endif
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#define CONFIG_BOOTDELAY 3
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2012-01-16 21:20:09 +00:00
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/*
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* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
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* Timeout 1 second.
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*/
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#define CONFIG_AIT_TIMER_TIMEOUT 0x186a00
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2011-11-01 20:00:35 +00:00
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_TIMESTAMP
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/* U-Boot memory configuration */
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#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
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#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
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#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
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#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
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/* Linux interfacing */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
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#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
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#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
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2012-01-16 21:20:09 +00:00
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#define MTDPARTS_DEFAULT \
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"mtdparts=" \
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"davinci_nand.0:" \
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"128k(spl)," \
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"384k(UBLheader)," \
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"1m(u-boot)," \
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"512k(env)," \
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"-(ubi)"
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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2011-11-01 20:00:35 +00:00
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_LOAD
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#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_POST_MEM_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
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#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
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#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE 12320
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_TEXT_BASE 0x81080000
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#endif
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#define CONFIG_SYS_NAND_BASE 0x02000000
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_ECCPOS { \
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24, 25, 26, 27, 28, \
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
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59, 60, 61, 62, 63 }
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCSIZE 0x200
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#define CONFIG_SYS_NAND_ECCBYTES 10
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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/*
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* RBL searches from Block n (n = 1..24)
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* so we can define, how many UBL Headers
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* we can write before the real spl code
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*/
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#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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/*
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* Post tests for memory testing
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*/
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY
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#define _POST_WORD_ADDR 0x0
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
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2012-01-16 21:20:09 +00:00
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
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2011-11-01 20:00:35 +00:00
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/*
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* U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
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* done in board_init_f from c code.
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*/
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* for UBL header */
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#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
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#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
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#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
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#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
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#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
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/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
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#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
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/*
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* POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
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|
|
|
* interface clk)
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
|
|
|
|
|
/* POST DIV 680/2 = 340Mhz -> VPSS */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
|
|
|
|
|
/* POST DIV 680/9 = 75.6 Mhz -> VENC */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
|
|
|
|
|
/*
|
|
|
|
|
* POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
|
|
|
|
|
* down to 340 Mhz)
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
|
|
|
|
|
/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
|
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|
|
|
#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
|
|
|
|
|
/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
|
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|
|
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|
|
#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
|
|
|
|
|
/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
|
|
|
|
|
/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
|
|
|
|
|
/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* READ LATENCY 7 (CL + 2)
|
|
|
|
|
* CONFIG_PWRDNEN = 1
|
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|
|
* CONFIG_EXT_STRBEN = 1
|
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|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
|
|
|
|
|
| DV_DDR_PHY_EXT_STRBEN \
|
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|
|
| DV_DDR_PHY_PWRDNEN \
|
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|
|
|
| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
|
|
|
|
|
* T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
|
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|
|
|
* T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
|
|
|
|
|
* T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
|
|
|
|
|
* T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
|
|
|
|
|
* T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
|
|
|
|
|
* T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
|
|
|
|
|
* T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
|
|
|
|
|
| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
|
|
|
|
|
| (4 << DV_DDR_SDTMR1_RP_SHIFT) \
|
|
|
|
|
| (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
|
|
|
|
|
| (5 << DV_DDR_SDTMR1_WR_SHIFT) \
|
|
|
|
|
| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
|
|
|
|
|
| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
|
|
|
|
|
| (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
|
|
|
|
|
| (2 << DV_DDR_SDTMR1_WTR_SHIFT))
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
|
|
|
|
|
* T_XP = tCKE - 1 = 3 - 2
|
|
|
|
|
* T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
|
|
|
|
|
* T_XSRD = txsrd - 1 = 200 - 1
|
|
|
|
|
* T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
|
|
|
|
|
* T_CKE = tcke - 1 = 3 - 1
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
|
|
|
|
|
| (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
|
|
|
|
|
| (2 << DV_DDR_SDTMR2_XP_SHIFT) \
|
|
|
|
|
| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
|
|
|
|
|
| (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
|
|
|
|
|
| (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
|
|
|
|
|
| (2 << DV_DDR_SDTMR2_CKE_SHIFT))
|
|
|
|
|
|
|
|
|
|
/* PR_OLD_COUNT = 0xfe */
|
|
|
|
|
#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
|
|
|
|
|
/* refresh rate = 0x768 */
|
|
|
|
|
#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
|
|
|
|
|
| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
|
|
|
|
|
| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
|
|
|
|
|
| (5 << DV_DDR_SDCR_CL_SHIFT) \
|
|
|
|
|
| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
|
|
|
|
|
| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
|
|
|
|
|
| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
|
|
|
|
|
| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
|
|
|
|
|
| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
|
|
|
|
|
| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
|
|
|
|
|
| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_DM36x_AWCCR 0xff
|
|
|
|
|
#define CONFIG_SYS_DM36x_AB1CR 0x40400204
|
|
|
|
|
#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
|
|
|
|
|
|
|
|
|
|
/* All Video Inputs */
|
|
|
|
|
#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
|
|
|
|
|
/*
|
|
|
|
|
* All Video Outputs,
|
|
|
|
|
* GPIO 86, 87 + 90 0x0000f030
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
|
|
|
|
|
#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
|
|
|
|
|
/*
|
|
|
|
|
* SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
|
|
|
|
|
* GPIO 25 0x60000000
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
|
|
|
|
|
/*
|
|
|
|
|
* MMC/SD0 instead of MS, SPI0
|
|
|
|
|
* GPIO 34 0x0000c000
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Default environment settings
|
|
|
|
|
*/
|
|
|
|
|
#define xstr(s) str(s)
|
|
|
|
|
#define str(s) #s
|
|
|
|
|
|
|
|
|
|
#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
|
|
|
|
|
/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
|
|
|
|
|
#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
|
|
|
|
|
/*
|
|
|
|
|
* (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
|
|
|
|
|
* CONFIG_SYS_NAND_PAGE_SIZE))
|
|
|
|
|
*/
|
|
|
|
|
#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
|
|
|
|
|
|
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
|
|
"u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
|
|
|
|
|
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
|
2012-01-16 21:20:09 +00:00
|
|
|
"load=tftp ${u_boot_addr_r} ${u-boot}\0" \
|
2011-11-01 20:00:35 +00:00
|
|
|
"pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
|
2012-01-16 21:20:09 +00:00
|
|
|
"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
|
|
|
|
|
"nand write ${u_boot_addr_r} 20000 ${pagesz};" \
|
2011-11-01 20:00:35 +00:00
|
|
|
"nandrbl uboot\0" \
|
2012-01-16 21:20:09 +00:00
|
|
|
"writenand_spl=nandrbl rbl;nand erase 0 3000;" \
|
2011-11-01 20:00:35 +00:00
|
|
|
"nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
|
2012-01-16 21:20:09 +00:00
|
|
|
" 0 3000;nandrbl uboot\0" \
|
2011-11-01 20:00:35 +00:00
|
|
|
"writeuboot=nandrbl uboot;" \
|
|
|
|
|
"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
|
|
|
|
|
xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
|
|
|
|
|
";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
|
|
|
|
|
" " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
|
|
|
|
|
xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
|
|
|
|
|
"update=run load writenand_spl writeuboot\0" \
|
2012-01-16 21:20:09 +00:00
|
|
|
"bootcmd=run net_nfs\0" \
|
|
|
|
|
"rootpath=/opt/eldk-arm/arm\0" \
|
|
|
|
|
"mtdids=" MTDIDS_DEFAULT "\0" \
|
|
|
|
|
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
|
|
|
|
"netdev=eth0\0" \
|
|
|
|
|
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
|
|
|
|
"addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \
|
|
|
|
|
"addcon=setenv bootargs ${bootargs} console=ttyS0," \
|
|
|
|
|
"${baudrate}n8\0" \
|
|
|
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
|
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
|
|
|
":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \
|
2011-11-01 20:00:35 +00:00
|
|
|
"rootpath=/opt/eldk-arm/arm\0" \
|
2012-01-16 21:20:09 +00:00
|
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
|
|
|
"nfsroot=${serverip}:${rootpath}\0" \
|
|
|
|
|
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
|
|
|
|
|
"kernel_addr_r=80600000\0" \
|
|
|
|
|
"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
|
|
|
|
|
"ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \
|
|
|
|
|
"ubifsload ${kernel_addr_r} boot/uImage\0" \
|
|
|
|
|
"fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
|
|
|
|
|
"img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
|
|
|
|
|
"img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0" \
|
|
|
|
|
"header_addr=20000\0" \
|
|
|
|
|
"img_writeheader=nandrbl rbl;" \
|
|
|
|
|
"nand erase ${header_addr} ${pagesz};" \
|
|
|
|
|
"nand write ${img_addr_r} ${header_addr} ${pagesz};" \
|
|
|
|
|
"nandrbl uboot\0" \
|
|
|
|
|
"img_writespl=nandrbl rbl;nand erase 0 3000;" \
|
|
|
|
|
"nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
|
|
|
|
|
"img_writeuboot=nandrbl uboot;" \
|
|
|
|
|
"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
|
|
|
|
|
xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
|
|
|
|
|
";nand write ${img_addr_r} " \
|
|
|
|
|
xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
|
|
|
|
|
xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
|
|
|
|
|
"img_writedfenv=ubi part ubi 2048;" \
|
|
|
|
|
"ubi write ${img_addr_r} default ${filesize}\0" \
|
|
|
|
|
"img_volume=rootfs1\0" \
|
|
|
|
|
"img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};" \
|
|
|
|
|
"ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
|
|
|
|
|
"load_img=tftp ${fit_addr_r} ${img_file}\0" \
|
|
|
|
|
"net_nfs=run load_kernel; " \
|
|
|
|
|
"run nfsargs addip addcon addmtd addmisc;" \
|
|
|
|
|
"bootm ${kernel_addr_r}\0" \
|
|
|
|
|
"ubi_ubi=run ubi_load_kernel; " \
|
|
|
|
|
"run ubiargs addip addcon addmtd addmisc;" \
|
|
|
|
|
"bootm ${kernel_addr_r}\0" \
|
|
|
|
|
"ubiargs=setenv bootargs ubi.mtd=4,2048" \
|
|
|
|
|
" root=ubi0:${img_volume} rw rootfstype=ubifs\0" \
|
|
|
|
|
"app_reset=no\0" \
|
|
|
|
|
"dvn_app_vers=void\0" \
|
|
|
|
|
"dvn_boot_vers=void\0" \
|
|
|
|
|
"savenewvers=run savetmpparms restoreparms; saveenv;" \
|
|
|
|
|
"run restoretmpparms\0" \
|
|
|
|
|
"savetmpparms=setenv y_ipaddr ${ipaddr};" \
|
|
|
|
|
"setenv y_netmask ${netmask};" \
|
|
|
|
|
"setenv y_serverip ${serverip};" \
|
|
|
|
|
"setenv y_gatewayip ${gatewayip}\0" \
|
|
|
|
|
"saveparms=setenv x_ipaddr ${ipaddr};" \
|
|
|
|
|
"setenv x_netmask ${netmask};" \
|
|
|
|
|
"setenv x_serverip ${serverip};" \
|
|
|
|
|
"setenv x_gatewayip ${gatewayip}\0" \
|
|
|
|
|
"restoreparms=setenv ipaddr ${x_ipaddr};" \
|
|
|
|
|
"setenv netmask ${x_netmask};" \
|
|
|
|
|
"setenv serverip ${x_serverip};" \
|
|
|
|
|
"setenv gatewayip ${x_gatewayip}\0" \
|
|
|
|
|
"restoretmpparms=setenv ipaddr ${y_ipaddr};" \
|
|
|
|
|
"setenv netmask ${y_netmask};" \
|
|
|
|
|
"setenv serverip ${y_serverip};" \
|
|
|
|
|
"setenv gatewayip ${y_gatewayip}\0" \
|
2011-11-01 20:00:35 +00:00
|
|
|
"\0"
|
|
|
|
|
|
|
|
|
|
/* USB Configuration */
|
|
|
|
|
#define CONFIG_USB_DAVINCI
|
|
|
|
|
#define CONFIG_MUSB_HCD
|
|
|
|
|
#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
|
|
|
|
|
USBPHY_PHY24MHZ)
|
|
|
|
|
|
|
|
|
|
#define CONFIG_CMD_USB /* include support for usb cmd */
|
|
|
|
|
#define CONFIG_USB_STORAGE /* MSC class support */
|
|
|
|
|
#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
|
|
|
|
|
#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
|
|
|
|
|
#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
|
|
|
|
|
|
|
|
|
|
#undef DAVINCI_DM365EVM
|
|
|
|
|
#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
|
|
|
|
|
#define PINMUX4_USBDRVBUS_BITSET 0x2000
|
|
|
|
|
|
|
|
|
|
#endif /* __CONFIG_H */
|
