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u-boot/arch/arm/mach-rockchip/Kconfig

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rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
if ARCH_ROCKCHIP
cosmetic: rockchip: sort socs according to numbers Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-15 22:17:15 +00:00
config ROCKCHIP_RK3036
bool "Support Rockchip RK3036"
select CPU_V7
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
select SUPPORT_SPL
select SPL
cosmetic: rockchip: sort socs according to numbers Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-15 22:17:15 +00:00
help
The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
rockchip: rk3188: Add core support Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Drop these defines from rk3188_common.h CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-18 18:46:36 +00:00
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
select TPL
rockchip: rk3188: enable remap function Most Rockchip socs have the ability to either map the bootrom or a sram area to the starting address of the cpu by flipping a bit in the GRF. Newer socs leave this untouched and mapped to the bootrom but the legacy loaders on rk3188 and before enabled the remap functionality and the current smp implementation in the Linux kernel also requires it to be enabled, to bring up secondary cpus. So to keep smp working in the kernel, mimic the behaviour of the legacy bootloaders and enable the remap functionality. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-05 22:19:36 +00:00
select BOARD_LATE_INIT
rockchip: rk3188: Add core support Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Drop these defines from rk3188_common.h CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-18 18:46:36 +00:00
select ROCKCHIP_BROM_HELPER
help
The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
video interfaces, several memory options and video codec support.
Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
UART, SPI, I2C and PWMs.
rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
rockchip: Clean up CPU selection In preparation for RK3368 and RK3399, which need to select ARM64, don't select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-14 03:09:26 +00:00
select CPU_V7
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
select SUPPORT_SPL
select SPL
rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
help
The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
video interfaces supporting HDMI and eDP, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
arm: rockchip: Fix typo in ROCKCHIP_RK3288 help UART,s -> UARTs, to avoid this spreading via copy&paste. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-11-02 17:03:01 +00:00
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
config ROCKCHIP_RK3328
bool "Support Rockchip RK3328"
select ARM64
help
The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
video interfaces supporting HDMI and eDP, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
rockchip: config: rk3399: enable SPL config for evb-rk3399 Enable all the CONFIGs which need by SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip tag: Drop CONFIG_ROCKCHIP_DWMMC for now due to build error: Move changes to arch/arm/mach-rockchip/Kconfig to this patch: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-22 08:56:38 +00:00
select SUPPORT_SPL
select SPL
select SPL_SEPARATE_BSS
rockchip: spl: RK3399: use boot0 hook to create space for SPL magic The SPL binary needs to be prefixed with the boot magic ('RK33' for the RK3399) on the Rockchip platform and starts execution of the instruction word following immediately after this boot magic. This poses a challenge for AArch64 (ARMv8) binaries, as the .text section would need to start on the odd address, violating natural alignment (and potentially triggering a fault for any code that tries to access 64bit values embedded in the .text section). A quick and easy fix is to have the .text section include the 'RK33' magic and pad it with a boot0 hook to insert 4 bytes of padding at the start of the section (with the intention of having mkimage overwrite this padding with the appropriate boot magic). This avoids having to modify the linker scripts or more complex logic in mkimage. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-03-15 11:08:44 +00:00
select ENABLE_ARM_SOC_BOOT0_HOOK
rockchip: rk3399: spl: add UART0 support for SPL The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the serial line available via standardised pins on the edge connector and available on a RS232 connector). To support boards (such as the RK3399-Q7) that require UART0 as a debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate iomux setup to the rk3399 SPL code. As we are already touching this code, we also move the board-specific UART setup (i.e. iomux setup) into board_debug_uart_init(). This will be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT is set. As the RK3399 needs to use its board_debug_uart_init() function, we have Kconfig enable it by default for RK3399 builds. With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB are then update (the change for the RK3399-Q7 is left for later to not cause issues on applying the change). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-01 10:59:25 +00:00
select DEBUG_UART_BOARD_INIT
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
video interfaces supporting HDMI and eDP, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
rockchip: add option to change method of loading u-boot If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-12 11:09:49 +00:00
config ROCKCHIP_SPL_BACK_TO_BROM
bool "SPL returns to bootrom"
default y if ROCKCHIP_RK3036
rockchip: Move bootrom helper compilation to a hidden option Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers compilation of the bootrom hook-code as well as enabling the behaviour of loading the full U-Boot via the boot. New added socs may always need the bootrom code, while still being able to decide between loading U-Boot regularly or via the bootrom separately. So move the compilation of the bootrom code to a hidden option that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also be selected by other parts. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-02-18 18:46:25 +00:00
select ROCKCHIP_BROM_HELPER
rockchip: add option to change method of loading u-boot If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-12 11:09:49 +00:00
help
Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
rockchip: reserve memory for rk3399 ATF data There are 3 regions used by rk3399 ATF: - bl31 code, located at 0x10000; - cortex-m0 code and data, located at 0xff8c0000; - bl31 data, located at 0xff8c1000 ~ 0xff8c4000; SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory for ATF data, or else there will be memory corrupt after SPL loads the ATF image. More detail about cortex-M0 code in ATF: https://github.com/ARM-software/arm-trusted-firmware/commit/ 8382e17c4c6bffd15119dfce1ee4372e3c1a7890 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-04-20 09:03:46 +00:00
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0x4000
help
SPL may need reserve memory for firmware loaded by SPL, whose load
address is in IRAM and may overlay with SPL text area if not
reserved.
rockchip: Move bootrom helper compilation to a hidden option Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers compilation of the bootrom hook-code as well as enabling the behaviour of loading the full U-Boot via the boot. New added socs may always need the bootrom code, while still being able to decide between loading U-Boot regularly or via the bootrom separately. So move the compilation of the bootrom code to a hidden option that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also be selected by other parts. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-02-18 18:46:25 +00:00
config ROCKCHIP_BROM_HELPER
bool
Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled. Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled. Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-08-29 11:31:16 +00:00
config SPL_MMC_SUPPORT
default y if !ROCKCHIP_SPL_BACK_TO_BROM
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
source "arch/arm/mach-rockchip/rk3036/Kconfig"
rockchip: rk3188: Add core support Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Drop these defines from rk3188_common.h CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-18 18:46:36 +00:00
source "arch/arm/mach-rockchip/rk3188/Kconfig"
cosmetic: rockchip: sort socs according to numbers Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-15 22:17:15 +00:00
source "arch/arm/mach-rockchip/rk3288/Kconfig"
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
source "arch/arm/mach-rockchip/rk3328/Kconfig"
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
source "arch/arm/mach-rockchip/rk3399/Kconfig"
rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
endif
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