2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2016-05-07 14:46:31 +00:00
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/*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
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*/
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/* XHCI Controller 0:14.0 */
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Device (XHCI)
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{
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Name(_ADR, 0x00140000)
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/* Power Resources for Wake */
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Name(_PRW, Package() { 13, 3 })
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/* Highest D state in S3 state */
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Name(_S3D, 3)
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Device (RHUB)
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{
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Name(_ADR, 0x00000000)
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Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */
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Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */
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Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */
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Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */
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}
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}
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