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49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* T30 LGE X3 SPL stage configuration
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*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* (C) Copyright 2022
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* Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <common.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <linux/delay.h>
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#define MAX77663_I2C_ADDR (0x1C << 1)
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#define MAX77663_REG_SD0 0x16
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#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
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#define MAX77663_REG_SD1 0x17
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#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
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#define MAX77663_REG_LDO4 0x2B
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#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
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#define MAX77663_REG_GPIO1 0x37
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#define MAX77663_REG_GPIO1_DATA (0x0800 | MAX77663_REG_GPIO1)
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#define MAX77663_REG_GPIO4 0x3A
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#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
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void pmic_enable_cpu_vdd(void)
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{
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/* Set VDD_CORE to 1.200V. */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
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udelay(1000);
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/* Bring up VDD_CPU to 1.0125V. */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
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udelay(1000);
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/* Bring up VDD_RTC to 1.200V. */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
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udelay(10 * 1000);
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/* Set GPIO4 and GPIO1 states */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO1_DATA);
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}
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