mirror of
https://github.com/AsahiLinux/u-boot
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514 lines
13 KiB
C
514 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Menlosystems M53Menlo board
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*
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* Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
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* Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <asm/mach-imx/mx5_video.h>
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#include <asm/mach-imx/video.h>
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#include <asm/gpio.h>
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#include <asm/spl.h>
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#include <fdt_support.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <ipu_pixfmt.h>
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#include <linux/errno.h>
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#include <linux/fb.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <spl.h>
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#include <splash.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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static u32 mx53_dram_size[2];
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ulong board_get_usable_ram_top(ulong total_size)
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{
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/*
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* WARNING: We must override get_effective_memsize() function here
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* to report only the size of the first DRAM bank. This is to make
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* U-Boot relocator place U-Boot into valid memory, that is, at the
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* end of the first DRAM bank. If we did not override this function
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* like so, U-Boot would be placed at the address of the first DRAM
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* bank + total DRAM size - sizeof(uboot), which in the setup where
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* each DRAM bank contains 512MiB of DRAM would result in placing
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* U-Boot into invalid memory area close to the end of the first
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* DRAM bank.
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*/
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return PHYS_SDRAM_2 + mx53_dram_size[1];
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}
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int dram_init(void)
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{
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mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = mx53_dram_size[0];
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = mx53_dram_size[1];
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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if (port == 0) {
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/* USB OTG PWRON */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
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PAD_CTL_PKE |
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PAD_CTL_DSE_HIGH));
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gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
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/* USB OTG Over Current */
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
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} else if (port == 1) {
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/* USB Host PWRON */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
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PAD_CTL_PKE |
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PAD_CTL_DSE_HIGH));
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gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
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/* USB Host Over Current */
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
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}
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return 0;
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}
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#endif
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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/* MDIO pads */
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
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/* FEC 0 pads */
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
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/* FEC 1 pads */
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NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg = {
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MMC_SDHC1_BASE_ADDR,
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
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gpio_direction_input(IMX_GPIO_NR(1, 1));
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return !gpio_get_value(IMX_GPIO_NR(1, 1));
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}
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_DSE_HIGH)
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
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};
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esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
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return fsl_esdhc_initialize(bis, &esdhc_cfg);
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}
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#endif
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#ifdef CONFIG_VIDEO
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static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
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{
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static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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int ret;
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/* For ETM0430G0DH6 model, this must be enabled before the clock. */
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gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
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/*
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* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
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* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
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*/
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ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
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if (ret)
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puts("IPU: Failed to configure LDB clock\n");
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/* Configure CCM_CSCMR2 */
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clrsetbits_le32(&mxc_ccm->cscmr2,
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(0x7 << 26) | BIT(10) | BIT(8),
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(0x5 << 26) | BIT(10) | BIT(8));
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/* Configure LDB_CTRL */
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writel(0x201, 0x53fa8008);
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}
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static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
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{
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/* For ETM0430G0DH6 model, this must be enabled before the clock. */
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gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
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/*
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* Set LVDS clock to 9 MHz for the display. The PLL4 is set to
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* 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
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*/
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enable_lvds_clock(dev, 63);
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}
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static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
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{
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/*
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* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
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* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
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*/
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enable_lvds_clock(dev, 233);
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/* For ETM0700G0DH6 model, this may be enabled after the clock. */
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gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
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}
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static const char *lvds_compat_string;
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static int detect_lvds(struct display_info_t const *dev)
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{
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u8 touchid[23];
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u8 *touchptr = &touchid[0];
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int ret;
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ret = i2c_set_bus_num(0);
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if (ret)
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return 0;
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/* Touchscreen is at address 0x38, ID register is 0xbb. */
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ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
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if (ret)
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return 0;
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/* EP0430 prefixes the response with 0xbb, skip it. */
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if (*touchptr == 0xbb)
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touchptr++;
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/* Skip the 'EP' prefix. */
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touchptr += 2;
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ret = !memcmp(touchptr, &dev->mode.name[7], 4);
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if (ret)
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lvds_compat_string = dev->mode.name;
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return ret;
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}
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void board_preboot_os(void)
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{
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/* Power off the LCD to prevent awful color flicker */
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gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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if (lvds_compat_string)
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do_fixup_by_path_string(blob, "/panel", "compatible",
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lvds_compat_string);
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return 0;
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}
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struct display_info_t const displays[] = {
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{
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.bus = 0,
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.addr = 0,
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.detect = detect_lvds,
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.enable = enable_lvds_etm0430g0dh6,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.mode = {
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.name = "edt,etm0430g0dh6",
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.refresh = 60,
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.xres = 480,
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.yres = 272,
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.pixclock = 111111, /* picosecond (9 MHz) */
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.left_margin = 2,
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.right_margin = 2,
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.upper_margin = 2,
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.lower_margin = 2,
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.hsync_len = 41,
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.vsync_len = 10,
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.sync = 0x40000000,
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.vmode = FB_VMODE_NONINTERLACED
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}
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}, {
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.bus = 0,
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.addr = 0,
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.detect = detect_lvds,
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.enable = enable_lvds_etm0700g0dh6,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.mode = {
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.name = "edt,etm0700g0dh6",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30048, /* picosecond (33.28 MHz) */
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.left_margin = 40,
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.right_margin = 88,
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.upper_margin = 10,
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.lower_margin = 33,
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.hsync_len = 128,
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.vsync_len = 2,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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}
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}
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};
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size_t display_count = ARRAY_SIZE(displays);
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#endif
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#ifdef CONFIG_SPLASH_SCREEN
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static struct splash_location default_splash_locations[] = {
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{
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.name = "mmc_fs",
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.storage = SPLASH_STORAGE_MMC,
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.flags = SPLASH_STORAGE_FS,
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.devpart = "0:1",
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},
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};
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int splash_screen_prepare(void)
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{
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return splash_source_load(default_splash_locations,
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ARRAY_SIZE(default_splash_locations));
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}
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#endif
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#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c_pads[] = {
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/* I2C1 */
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NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
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/* I2C2 */
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NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
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}
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static void setup_iomux_video(void)
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{
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static const iomux_v3_cfg_t lcd_pads[] = {
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MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
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MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
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MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
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MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
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||
|
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
|
||
|
};
|
||
|
|
||
|
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||
|
}
|
||
|
|
||
|
static void setup_iomux_nand(void)
|
||
|
{
|
||
|
static const iomux_v3_cfg_t nand_pads[] = {
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
|
||
|
PAD_CTL_DSE_HIGH),
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
|
||
|
PAD_CTL_DSE_HIGH),
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
|
||
|
PAD_CTL_DSE_HIGH),
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
|
||
|
PAD_CTL_DSE_HIGH),
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
|
||
|
PAD_CTL_PUS_100K_UP),
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
|
||
|
PAD_CTL_PUS_100K_UP),
|
||
|
NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
|
||
|
PAD_CTL_DSE_HIGH),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
|
||
|
};
|
||
|
|
||
|
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
||
|
}
|
||
|
|
||
|
static void m53_set_clock(void)
|
||
|
{
|
||
|
int ret;
|
||
|
const u32 ref_clk = MXC_HCLK;
|
||
|
const u32 dramclk = 400;
|
||
|
u32 cpuclk;
|
||
|
|
||
|
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
|
||
|
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
|
||
|
gpio_direction_input(IMX_GPIO_NR(4, 0));
|
||
|
|
||
|
/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
|
||
|
cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
|
||
|
|
||
|
ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
|
||
|
if (ret)
|
||
|
printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
|
||
|
|
||
|
ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
|
||
|
if (ret) {
|
||
|
printf("CPU: Switch peripheral clock to %dMHz failed\n",
|
||
|
dramclk);
|
||
|
}
|
||
|
|
||
|
ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
|
||
|
if (ret)
|
||
|
printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
|
||
|
}
|
||
|
|
||
|
static void m53_set_nand(void)
|
||
|
{
|
||
|
u32 i;
|
||
|
|
||
|
/* NAND flash is muxed on ATA pins */
|
||
|
setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
|
||
|
|
||
|
/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
|
||
|
for (i = 0x4; i < 0x94; i += 0x18) {
|
||
|
clrbits_le32(WEIM_BASE_ADDR + i,
|
||
|
WEIM_GCR2_MUX16_BYP_GRANT_MASK);
|
||
|
}
|
||
|
|
||
|
mxc_set_clock(0, 33, MXC_NFC_CLK);
|
||
|
enable_nfc_clk(1);
|
||
|
}
|
||
|
|
||
|
int board_early_init_f(void)
|
||
|
{
|
||
|
setup_iomux_uart();
|
||
|
setup_iomux_fec();
|
||
|
setup_iomux_i2c();
|
||
|
setup_iomux_nand();
|
||
|
setup_iomux_video();
|
||
|
|
||
|
m53_set_clock();
|
||
|
|
||
|
mxc_set_sata_internal_clock();
|
||
|
|
||
|
/* NAND clock @ 33MHz */
|
||
|
m53_set_nand();
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int board_init(void)
|
||
|
{
|
||
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int checkboard(void)
|
||
|
{
|
||
|
puts("Board: Menlosystems M53Menlo\n");
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* NAND SPL
|
||
|
*/
|
||
|
#ifdef CONFIG_SPL_BUILD
|
||
|
void spl_board_init(void)
|
||
|
{
|
||
|
setup_iomux_nand();
|
||
|
m53_set_clock();
|
||
|
m53_set_nand();
|
||
|
}
|
||
|
|
||
|
u32 spl_boot_device(void)
|
||
|
{
|
||
|
return BOOT_DEVICE_NAND;
|
||
|
}
|
||
|
#endif
|